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Title:
INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS5929454
Kind Code:
A
Abstract:

PURPOSE: To supply an electrically stable IC by reducing even the noises of supply voltage due to inductance formed in a bonding wire in a logic type integrated circuit with a large number of output buffer circuits.

CONSTITUTION: A signal line for constituting the logic IC is formed onto a silicon substrate 1, and a plasma nitride film 2 is formed in order to insulate and isolate a signal wiring and supply wirings 3, 4. One supply wiring 3 is formed to approximately the whole surface of the IC with Al on the inslating film 2, an Al2O3 film 5 is formed to the surface through an anoidic oxidation method, and the other supply wiring 4 is formed to approximately the whole surface of the IC. Consequently, a capacitor C is set up between a supply terminal VCC on the IC and a GND, and the capacitor C feeds charges required for a current change in the IC, and reduces current changes in inductances L1, L2. Accordingly, the supply terminal VCC in the IC and the GND are supplied with stable potential of small noises. Voltage noises are reduced with the increase of the capacitance C because a voltage change of the capacitor C is ΔI.Δt/C.


Inventors:
OKADA KENJI
ITOU SOUICHI
Application Number:
JP13937282A
Publication Date:
February 16, 1984
Filing Date:
August 11, 1982
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/8222; H01L27/06; H01L29/08; H01L29/41; (IPC1-7): H01L27/08; H01L29/40
Attorney, Agent or Firm:
Uchihara Shin



 
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