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Patent Searching and Data


Title:
TRANSFER SYSTEM FOR ARITHMETIC DATA
Document Type and Number:
Japanese Patent JPS58140858
Kind Code:
A
Abstract:

PURPOSE: To speed up arithmetic processing by adding an information processor which has one-word, n-byte constitution and performs word-by-word data transfer and hardware dedicated to data positioning and code extension.

CONSTITUTION: Data read out of a main storage device, word by word, is stored in a data register 1 and the low-order (l) bits of a readout address are stored in a register 2. For arithmetic processing, the data is sent from the register 1 to a function circuit 3. The circuit 3 is given the position of necessary data in one read word by the register 2 and also supplied with the length of data to be processed and an instruction for arithmetic format through a line 15. The circuit 3 when commanded to perform k-byte arithmetic shifts the data in the register 1 to right by n-(m+k) bytes according to the address (m) set in the register 2 to set a sign in the left-hand side (n-k) bytes, and the resulting data is supplied to a logical operation circuit 4 to perform the prescribed arithmetic. Thus, program steps are decreased to realize high-speed processing.


Inventors:
SAKAI TAKAHIKO
Application Number:
JP2410482A
Publication Date:
August 20, 1983
Filing Date:
February 17, 1982
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F12/00; G06F9/308; G06F12/04; (IPC1-7): G06F13/00
Attorney, Agent or Firm:
Takehiko Suzue