Title:
VOLTAGE SUBTRACTER/ADDER AND MOS DIFFERENTIAL AMPLIFIER CIRCUIT TO ACHIEVE THE SAME
Document Type and Number:
Japanese Patent JP2002076800
Kind Code:
A
Abstract:
To provide a MOS differential amplifier circuit having a subtracter/ adder function, which has a good linearity over a wide input voltage range and is formed on the semiconductor integrated circuit.
A voltage subtracter/adder of this invention is so constituted that the gates of transistors M1 and M2 constitute a pair of inputs and drains constitute a pair of subtraction outputs respectively, that addition output terminals are formed by commonly connecting the sources, and that the sum of the current flowing in the transistors M1 and M2 increase in proportion to an input differential voltage.
More Like This:
JPH06150033 | WEIGHTED ADDER CIRCUIT |
JPH0944582 | WEIGHTED ADDITION CIRCUIT |
Inventors:
KIMURA KATSUHARU
Application Number:
JP2000260806A
Publication Date:
March 15, 2002
Filing Date:
August 30, 2000
Export Citation:
Assignee:
NEC CORP
International Classes:
G06G7/14; H03F1/32; H03F3/45; H03G3/10; (IPC1-7): H03F3/45; G06G7/14; H03F1/32; H03G3/10
Domestic Patent References:
JPH11251848A | 1999-09-17 | |||
JPH11251853A | 1999-09-17 | |||
JPH11102407A | 1999-04-13 | |||
JPS6284609A | 1987-04-18 | |||
JPH07336163A | 1995-12-22 | |||
JPH0832372A | 1996-02-02 | |||
JPH02240785A | 1990-09-25 |
Attorney, Agent or Firm:
Takahashi Isamu
Previous Patent: OFFSET CORRECTION APPARATUS IN DIFFERENTIAL AMPLIFIER AND THE METHOD OF OFFSET CORRECTION
Next Patent: DIFFERENTIAL AMPLIFIER
Next Patent: DIFFERENTIAL AMPLIFIER