Title:
The data output timing control circuit of a semiconductor device
Document Type and Number:
Japanese Patent JP5955764
Kind Code:
B2
Abstract:
A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.
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Inventors:
Kyung Hoon Kim
Application Number:
JP2012281964A
Publication Date:
July 20, 2016
Filing Date:
December 26, 2012
Export Citation:
Assignee:
SK hynix Inc.
International Classes:
G06F12/00; G11C11/413
Domestic Patent References:
| JP201020888A | ||||
| JP200871018A |
Foreign References:
| US20110187427 |
Attorney, Agent or Firm:
Kunio Ueda
Noriharu Fujita
Kawakami Miki
Noriharu Fujita
Kawakami Miki