Title:
INFORMATION PROCESSING SYSTEM, DIAGNOSTIC METHOD FOR TRANSISTOR CIRCUIT, AND PROGRAM
Document Type and Number:
Japanese Patent JP2017182670
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a transistor circuit that can update a logical value in a control register in a short time.SOLUTION: A transistor circuit includes a majority decision reading unit and a writing unit. The majority decision reading unit obtains logical values from three registers that respectively correspond to three logical circuits having an identical structure, and makes a majority decision. The writing unit writes, on the basis of a result of the majority decision made by the majority decision reading unit, a logical value indicated by the result in the three registers.SELECTED DRAWING: Figure 3
More Like This:
Inventors:
FUNAKOSHI HISAFUMI
Application Number:
JP2016072577A
Publication Date:
October 05, 2017
Filing Date:
March 31, 2016
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F11/18; H03K19/003; H03K19/173
Domestic Patent References:
| JPS5739465A | 1982-03-04 | |||
| JP2011216020A | 2011-10-27 | |||
| JP2010008881A | 2010-01-14 |
Other References:
丸本 耕平 他: "「故障挿入によるＴＭＲプロセッサの耐縮退故障性評価」", ＦＩＴ２００７ 第６回情報科学技術フォーラム 一般講演論文集 第１分冊, JPN6016049878, 22 August 2007 (2007-08-22), JP, pages 225 - 226, ISSN: 0003469949
一ノ宮 佳裕 他: "「ＳＲＡＭ型ＦＰＧＡの部分再構成によるソフトコアプロセッサの高信頼化」", 電子情報通信学会論文誌, vol. 第J92-D巻 第12号, JPN6016049880, 1 December 2009 (2009-12-01), JP, pages 2105 - 2113, ISSN: 0003469950
一ノ宮 佳裕 他: "「ＳＲＡＭ型ＦＰＧＡの部分再構成によるソフトコアプロセッサの高信頼化」", 電子情報通信学会論文誌, vol. 第J92-D巻 第12号, JPN6016049880, 1 December 2009 (2009-12-01), JP, pages 2105 - 2113, ISSN: 0003469950
Attorney, Agent or Firm:
Sumio Tanai
Ryuichiro Mori
Yasushi Matsunuma
Eisuke Ito
Ryuichiro Mori
Yasushi Matsunuma
Eisuke Ito