Title:
半導体装置、記憶装置、電子機器、又は該半導体装置の駆動方法
Document Type and Number:
Japanese Patent JP6773521
Kind Code:
B2
Abstract:
A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor are electrically connected to a first terminal of a capacitor, and a control circuit is electrically connected to a second terminal of the capacitor. The control circuit supplies a first potential to the second terminal of the capacitor, in other words, adds a value corresponding to the first potential to the value of first data previously retained in the gate of the second transistor in order to obtain second data. In the second transistor, the second data, specifically, a third potential commensurate with the potential of the gate will be output from a second terminal when a second potential is supplied to a first terminal.
Inventors:
Takanori Matsuzaki
Application Number:
JP2016214459A
Publication Date:
October 21, 2020
Filing Date:
November 01, 2016
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G11C11/56; G06F12/00; G06G7/14; G11C11/405
Domestic Patent References:
| JP2014209402A | ||||
| JP200128443A |