Title:
半導体装置
Document Type and Number:
Japanese Patent JP7400057
Kind Code:
B2
Abstract:
A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.
Inventors:
Shintaro Harada
Yoshimoto Kurokawa
Ken Aoki
Yoshimoto Kurokawa
Ken Aoki
Application Number:
JP2022174098A
Publication Date:
December 18, 2023
Filing Date:
October 31, 2022
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/60; G06G7/14; G06G7/16; G06G7/184; G06N3/063; G11C11/405; G11C11/54; G11C11/56; H01L29/786; H10B12/00; H10B41/70
Domestic Patent References:
| JP3080379A | ||||
| JP4067259A | ||||
| JP2016157506A |
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