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Patent Searching and Data


Title:
METHOD FOR MANUFACTURING MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2024/089809
Kind Code:
A1
Abstract:
The present invention comprises: a step of forming a first memory cell by forming, from bottom to top, a first N+layer 2a, a first P-layer 3, a first gate insulating layer 5, a first gate conductor layer 6, a second gate conductor layer 8, and a second N+layer 2b on a first P-layer substrate 1, and forming a second conductor layer 11 connected to a second N+layer 2b and extending horizontally, a first material layer 12 on the first conductor layer 11, and a second material layer 13 on the second N+layer 2b; a step of forming a second memory cell having the same structure as the first memory cell on a second P-layer substrate 1a; and forming a two-stage memory cell by aligning the positions of the first material layer 12 and the third material layer 12a, aligning the positions of the second material layer 13 and the fourth material layer 13a, and attaching the first memory cell and the second memory cell to each other. One or both of the first and third material layers 12 and 12a and the second and fourth material layers 13 and 13a can be oxide material layers.

Inventors:
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
Application Number:
PCT/JP2022/039959
Publication Date:
May 02, 2024
Filing Date:
October 26, 2022
Export Citation:
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Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
International Classes:
H10B12/00
Domestic Patent References:
WO2022137607A12022-06-30
WO2014184933A12014-11-20
Foreign References:
JP2018152419A2018-09-27
JP2008172164A2008-07-24
JP2003188279A2003-07-04
JP2008147514A2008-06-26
US20200135863A12020-04-30
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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