Title:
PROTECTIVE MATERIAL TO PREVENT SHORT CIRCUITS IN THREE-DIMENSIONAL MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/022319
Kind Code:
A3
Abstract:
In a three-dimensional stacked non-volatile memory device, a short circuit is prevented in a select gate layer by providing a protective material such as a diode, capacitor, linear resistor or varistor between select gate lines and a remaining portion of the select gate layer. Charges which are accumulated in the select gate lines due to plasma etching are therefore prevented from discharging through the remaining portion in a short circuit path when the select gate lines are driven. The protective material can comprise a p-n diode, an n-i-n or p-i-p resistor, a thin oxide layer between doped polysilicon layers in a capacitor, or a variable-resistance material such as ZnO2 between oxide layers in a varistor.
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Inventors:
YUAN JIAHUI (US)
PACHAMUTHU JAYAVEL (US)
DONG YINGDA (US)
ZHAO WEI (US)
PACHAMUTHU JAYAVEL (US)
DONG YINGDA (US)
ZHAO WEI (US)
Application Number:
PCT/US2015/042302
Publication Date:
May 06, 2016
Filing Date:
July 27, 2015
Export Citation:
Assignee:
SANDISK TECHNOLOGIES INC (US)
International Classes:
G01R31/26; H01L27/115; G01R31/50
Domestic Patent References:
| WO2010018888A1 | 2010-02-18 |
Foreign References:
| US20130234338A1 | 2013-09-12 | |||
| US20130032875A1 | 2013-02-07 | |||
| US20090268523A1 | 2009-10-29 |
Attorney, Agent or Firm:
MAGEN, Burt (575 Market Street Suite 375, San Francisco California, US)
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