Title:
SEMICONDUCTOR STRUCTURE AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/045262
Kind Code:
A1
Abstract:
Disclosed in embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises: a plurality of active regions; a bit line selection unit, comprising a first gate, a second gate, a third gate, and a fourth gate which are respectively located on the four active regions adjacent to each other, and a connecting line, wherein the first gate and the second gate intersect at a first node, the third gate and the fourth gate intersect at a second node, and the connecting line connects the first node and the second node; and a plurality of bit lines, each bit line comprising a first portion and a second portion and a connecting portion connecting the first portion and the second portion, each bit line being connected to one active region, different bit lines being connected to different active regions, and the first portion of any bit line being parallel to the second portion of the bit line adjacent thereto.
Inventors:
GAO YICHENG (CN)
CHA JAEYONG (CN)
CHA JAEYONG (CN)
Application Number:
PCT/CN2022/123987
Publication Date:
March 07, 2024
Filing Date:
October 09, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H10B12/00; G11C11/4097
Foreign References:
| CN1302085A | 2001-07-04 | |||
| CN1877835A | 2006-12-13 | |||
| US6380576B1 | 2002-04-30 | |||
| US20090218609A1 | 2009-09-03 | |||
| US20130264655A1 | 2013-10-10 | |||
| JP2010183015A | 2010-08-19 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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