SEMICONDUCTOR STRUCTURE AND MEMORY

WIPO Patent Application WO/2024/045264

A1

Disclosed in the embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises at least one sub-wordline driver, wherein the sub-wordline driver comprises: a plurality of first active areas; and a main wordline, which comprises a plurality of first gate electrodes and a plurality of second gate electrodes which are interconnected, the plurality of first gate electrodes corresponding to the plurality of first active areas, wherein extension directions of the plurality of first gate electrodes in the main wordline and/or extension directions of at least some of the second gate electrodes in the main wordline intersect with both a first direction and a second direction; and the first direction is parallel to extension directions of the first active areas, and the second direction is parallel to a plane where the first active areas are located, and is perpendicular to the first direction.

WO/2013/159307	SEMICONDUCTOR DEVICE INCLUDING ELECTROMAGNETIC ABSORPTION AND SHIELDING
WO/2021/080676	SEMICONDUCTOR APPARATUS HAVING STACKED DEVICES AND METHOD OF MANUFACTURE THEREOF
JPS5954255	LARGE SCALE INTEGRATED CIRCUIT

WU QILONG (CN)
LIU CHIH-CHENG (CN)
LEE TZUNG-HAN (CN)

PCT/CN2022/124056

March 07, 2024

October 09, 2022

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CXMT CORP (CN)

H01L27/02; G11C11/409; G11C11/4094

US20180182448A1	2018-06-28
CN113327635A	2021-08-31
CN114913891A	2022-08-16
US20180166119A1	2018-06-14

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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