SEMICONDUCTOR SUBSTRATE AND PROCESS FOR FABRICATING THE SAME

WIPO Patent Application WO/2005/104198

A1

A semiconductor substrate comprising a wafer, a first stepped structure consisting of a plurality of stepped portions formed on the wafer surface with a first area rate, a second stepped structure consisting of a plurality of stepped portions formed on the wafer surface with a second different area rate, and an interlayer insulation film having a planarization surface formed on the wafer surface to cover the first and second stepped structures. At least first and second film thickness monitor patterns are provided on the wafer surface while being covered with the interlayer insulation film. A first pattern group consisting of a plurality of different patterns is formed on the wafer surface to surround the first film thickness monitor pattern, and a second pattern group consisting of a plurality of different patterns is formed on the wafer surface to surround the second film thickness monitor pattern. On the wafer surface, the first film thickness monitor pattern and the first pattern group have a third area rate and the second film thickness monitor pattern and the second pattern group have a fourth area rate wherein the third and fourth area rates are different from each other.

YAEGASHI TETSUO (JP)
NAGAI KOUICHI (JP)

PCT/JP2004/005794

November 03, 2005

April 22, 2004

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FUJITSU LTD (JP)
YAEGASHI TETSUO (JP)
NAGAI KOUICHI (JP)

H01L21/304; H01L21/66; H01L21/8239; H01L23/544; H01L27/105; (IPC1-7): H01L21/304; H01L21/66; H01L21/8239; H01L27/105

JPH11219922A	1999-08-10
JP2001332556A	2001-11-30
JP2000058611A	2000-02-25
JP2001127014A	2001-05-11
JP2002083792A	2002-03-22
JP2003140319A	2003-05-14

Itoh, Tadahiko (Yebisu Garden Place Tower 20-3, Ebisu 4-chom, Shibuya-ku Tokyo 32, JP)

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