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JP7345191B2 |
A system (10) for convolving and adding frames of data comprises a first sensor-display device (14) and a second sensor display device (26). Each sensor display device (14, 26) comprises an array (80) of transmit-receive modules (82). Ea...
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JP2023128984A |
To address an issue that reduction of the power consumption is not sufficient in an existing semiconductor device.In the semiconductor device according to an embodiment, a memory cell is controlled so that operation processing is stopped...
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JP2023129201A |
To provide a semiconductor device equipped with a three-dimensional neural network using a three-dimensional silicon circuit network and independent of bits, and a method for manufacturing the same.One module containing three units in th...
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JP2023129271A |
To provide a method of using reduced read energy based on a partial sum.Embodiments include monitoring a partial sum of a multiply accumulate calculation for certain conditions. When the certain conditions are met, reduced read energy is...
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JP2023126751A |
To provide a semiconductor apparatus with a new configuration.A semiconductor apparatus includes a plurality of arithmetic circuits capable of switching between different arithmetic processing, a plurality of switch circuits capable of s...
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JP7340612B2 |
Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificia...
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JP7338876B2 |
Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators;...
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JP7337563B2 |
A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a functi...
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JP7337782B2 |
A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and c...
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JP7336819B2 |
Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the...
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JP2023117828A |
To provide a physical reservoir computing technology having high storage capacity.A computing device includes: an input circuit for generating a first voltage signal based on an input signal; a magnetic tunnel junction element for output...
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JP2023117922A |
To provide a machine learning method and a machine learning device in a neural network including a physical system that do not require a large operation cost and accurate information of the physical system for a training.The present inve...
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JP7330961B2 |
In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an in...
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JP7329151B2 |
Numerous examples of a precision programming apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) arra...
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JP2023534389A |
The present invention comprises a semiconductor layer (101, 201), a source electrode (102, 202) connected to the semiconductor layer (101, 201) and a drain electrode (103, 203) connected to the semiconductor layer (101, 201). ), wherein ...
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JP2023534314A |
A system and method are disclosed for accelerating a multiply-accumulate (MAC) floating point unit during training of a deep learning network. The method includes receiving a first input data stream A and a second input data stream B, an...
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JP2023533846A |
Computer-implemented method, system, and computer program product embodiments are provided for updating an analog crossbar array. Embodiments include receiving a number used for matrix multiplication represented using pulse generation fo...
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JP2023532877A |
A hybrid analog-digital processing system is described. One example of a hybrid analog-digital processing system includes a photonic accelerator configured to perform matrix-vector multiplication using light. A photonic accelerator exhib...
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JP7314286B2 |
A neural network device with synapses having memory cells each having source and drain regions in a semiconductor substrate with a channel region extending there between, a floating gate over an entirety of the channel region, and a firs...
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JP7311095B2 |
An apparatus of analog-neuron includes a synapse circuit for performing arithmetic processing for multiplying an input signal that arrives at an input terminal by a weight value, a synapse output holding means for holding an output signa...
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JP7308290B2 |
Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a...
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JP7306725B2 |
A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node a...
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JP2023093463A |
To provide a bit line decoder circuit, an analog neuromorphic memory system, a word line driver, and a current voltage circuit for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network.A vector-by-matrix ...
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JP7301295B2 |
To provide an information processing device capable of executing a reservoir calculation model on which an integrated circuit can be loaded.An information processing device 10 includes an intermediate layer 13 which is coupled to a plura...
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JP2023088730A |
To provide a calculation system in which multiple signals are efficiently available.According to one embodiment, a calculation system including multiple multiplying elements, multiple adding elements, a first processing circuit, and a se...
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JP2023088841A |
To provide a neural network circuit and device.A neural network circuit 100 includes: a synapse memory array 110 that is arranged along J output lines, includes a resistive memory element having one of a first resistance value and a seco...
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JP2023525950A |
A sensor assembly for determining one or more characteristics of a local area is presented herein. The sensor assembly includes multiple stacked sensor layers. A first sensor layer of the plurality of stacked sensor layers on top of the ...
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JP2023084094A |
To provide a circuit and a system which decreases a circuit area, improves power consumption, and decreases insufficiency.In a hardware accelerator for a neural network, a convolutional block using a pseudo multiplication circuit for imp...
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JP2023524822A |
A computer-implemented method is presented for performing matrix sketching by utilizing an analog crossbar architecture. The method includes low-rank updating a first matrix over a first time period, copying the first matrix to a dynamic...
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JP7289802B2 |
To provide a low-power and high-accuracy reservoir computer.In a reservoir computer which executes learning computation and inference computation, a reservoir section having reservoir neurons is formed of analog circuits. The reservoir c...
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JP7289976B2 |
A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a co...
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JP2023524219A |
A photonic processor is described. Photonic processors described herein are configured to perform matrix multiplication (eg, matrix-vector multiplication). Matrix multiplication is decomposed into scalar multiplication and scalar additio...
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JP2023078182A |
To provide an arithmetic device with small power consumption and an electronic device, to provide an arithmetic device with possible high-speed operation and an electronic device, and to provide an arithmetic device capable of suppressin...
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JP7288047B2 |
Zero-shifting techniques in analog crosspoint arrays are provided. In one aspect, an analog array-based vector-matrix multiplication includes: a weight array connected to a reference array, each including a crossbar array having a set of...
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JP7286006B2 |
A system for performing learning is described. The system includes a linear programmable network layer and a nonlinear activation layer. The linear programmable network layer includes inputs, outputs and linear programmable network compo...
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JP2023075088A |
To provide a semiconductor device with a new structure.A module included in a semiconductor device is composed of: n (n is a natural number) neuron circuits NU; m×n (m is a natural number) synaptic circuits SU; and m error circuits EU. ...
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JP2023075106A |
To reduce the circuit scale of a semiconductor device that can perform arithmetic processing of analog data.A semiconductor device 10 comprises: a storage circuit 11 (MEM); a reference storage circuit 12 (RMEM); a circuit 13; a circuit 1...
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JP7283477B2 |
This multiply-accumulate operation device executes a multiply-accumulate operation with an analog circuit, and includes: a plurality of input lines; a plurality of multiplication units; an accumulation unit; a charging unit; and an outpu...
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JP2023521888A |
An Ising machine having a network of resistive-coupled circuit nodes, wherein at least one node has a voltage across its terminals representing a state variable of the node and a voltage across at least one other node of the network. a r...
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JP2023073196A |
To provide a computing device for performing a digital pulse-based crossbar operation and a method of operating the same.The computing device includes: a plurality of input lines to which a pulse is selectively input in a sequential mann...
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JP2023521341A |
A differential mixed signal logic processor is provided. A differential mixed-signal logic processor includes multiple mixed-signal multiplier branches for multiplication of an analog value A and an N-bit digital value B. Each of the plu...
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JP7277667B1 |
An optical arithmetic device (1) comprises an optical modulation element (11) including a plurality of cells whose modulation amounts can be independently set, and a mirror (12). N arithmetic areas A1, A2, . . . AN are set in the light m...
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JP7274070B1 |
A nonlinear function operation device, which is one aspect of the present invention, converts an input signal into time information using a nonlinear operation unit in which an internal physical quantity autonomously changes according to...
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JP2023064732A |
To provide synapse circuits and methods for implementing Bayesian neural networks.A synapse circuit 202 for a Bayesian neural network is provided, comprising: a first resistive memory device 302 coupling a second voltage rail (Vread) to ...
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JP7271463B2 |
A synaptic circuit according to an embodiment includes: a weight current circuit that applies a weight current corresponding to a weight value; an input switch that switches whether or not to cause the weight current circuit to apply the...
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JP2023518349A |
The optical synapse includes a memristive device for non-volatile storage of synaptic weights dependent on the resistance of the device and an optical modulator for volatile modulation of optical transmission in the waveguide. The memris...
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JP7266330B2 |
The present invention discloses a neural network training method for a memristor memory for memristor errors, which is mainly used for solving the problem of decrease in inference accuracy of a neural network based on the memristor memor...
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JP7263241B2 |
Computations in Artificial neural networks (ANNs) are accomplished using simple processing units, called neurons, with data embodied by the connections between neurons, called synapses, and by the strength of these connections, the synap...
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JP2023516343A |
An in-memory computing architecture and method are provided for performing multiply-accumulate operations. The method includes sequentially shifting bits of a first input byte into each row of an array of memory cells arranged in rows an...
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JP7259253B2 |
An artificial neural network circuit includes a crossbar circuit, and a processing circuit. The crossbar circuit transmits a signal between layered neurons of an artificial neural network. The crossbar circuit includes input bars, output...
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