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JP2023554501A |
A linear multiplier configured to generate an output current representing the product of a first input voltage and a second input voltage. a first transconductance stage configured to receive a first input voltage and output a first set ...
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JP7406055B2 |
To provide an exponential function generating circuit having a positive exponentiation with a circuit for generating a voltage and a clock frequency of an exponential function of high accuracy with a smaller number of elements than befor...
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JP7405493B2 |
In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a f...
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JP7403739B2 |
This intention determination device selects one option from among 2n options (where n is a natural number) for which a reward can be stochastically received. The intention determination device: forms a virtual binary tree by using 2n-1 c...
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JP2023552971A |
The neural network device includes a first plurality of synaptic network capacitors, the synaptic network capacitors of the first plurality of synaptic network capacitors sharing a first output terminal. The neural network device further...
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JP2023179078A |
To provide a technique capable of suppressing power consumption while suppressing an increase in a time required for computing in the case that the power consumption or the like increases.Arithmetic units 100, 100B, 100C, 100D include: a...
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JP7400057B2 |
A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and re...
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JP7399517B2 |
Disclosed are a parallel acceleration method for a memristor-based neural network, a parallel acceleration processor based on a memristor-based neural network and a parallel acceleration device based on a memristor-based neural network. ...
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JP7398841B2 |
This brain-type information processing device has an analog resistance changing element composed of a pair of electrodes and an oxide layer provided between the pair of electrodes, and a drive circuit that superimposes and supplies volta...
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JP7398552B2 |
Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits ...
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JP7397944B2 |
An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a posit...
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JP2023175738A |
To provide a semiconductor device capable of reducing power consumption and storing data imitating a human brain.The semiconductor device includes a control unit, a storage unit, and a sensor unit. The storage unit includes a storage cir...
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JP7394827B2 |
Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation ...
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JP2023173393A |
To provide a product sum circuit capable of being used for neuron computing and a neural network including the product sum circuit.A product sum circuit 10 is a circuit for performing product-sum operations. The product sum circuit 10 in...
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JP7394197B2 |
An electronic device capable of efficiently recognizing a handwritten character is provided.The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display p...
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JP2023550689A |
Neuromorphic storage elements may include memristors, and a plurality of neuromorphic storage elements and methods for operating them may be provided. The memristor includes an input signal terminal, an output signal terminal, and a cont...
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JP2023171698A |
To provide an information storage system which simulates a neural network on a silicon chip without using a bit.A neural network has: a plurality of islands periodically disposed in a first axis direction and a second axis direction on a...
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JP7391097B2 |
A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate...
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JP7391215B2 |
Disclosed are an optical computing device and an optical signal processing method. The optical computing device includes a parametric oscillator array, an interaction computing matrix connected to the parametric oscillator array, a first...
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JP2023550308A |
The system includes a floating point calculation unit configured to perform a dot product operation according to the first floating point value and the second floating point value, and detection logic operably coupled to the floating poi...
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JP7389812B2 |
A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as ...
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JP2023169170A |
To provide a precise programming algorithm and device for precisely and rapidly depositing precise amounts of charge on a floating gate of a non-volatile memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neura...
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JP2023169189A |
To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.A photonic neural network system 10 for convolving and adding fram...
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JP2023169224A |
To provide a vector computation unit configured to enable parallel processing and pipelining of neural network computation thereby achieving high-speed execution.An architecture 600 for executing neural network computation for a neural n...
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JP2023169120A |
To provide a semiconductor device low in power consumption and resistant to high temperature.A semiconductor device has a first layer, and a second layer positioned above the first layer. The first layer has a first cell and first to thi...
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JP2023169190A |
To provide a system and method, which greatly increase speed, resolution, and power efficiency as compared to digital spatial convolutions for optically processing images.A photonic neural network system 10 for convolving and adding fram...
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JP2023548772A |
distributing the multiply-accumulate current across the segment mirrors by providing a circuit that includes an array of resistive elements, the array including rows and columns and a first stage current mirror, each of the first stage c...
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JP2023166390A |
To provide a semiconductor device capable of product-sum operations in which dispersion in transistor characteristics is reduced.A semiconductor device has: a first circuit including a drive unit, a correction unit, and a holding unit; a...
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JP7384925B2 |
Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to anal...
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JP7383528B2 |
A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in respon...
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JP2023547800A |
A method for artificial neural network training is presented. The method is to store weight values in an array of resistive processing unit (RPU) devices, the array of RPU devices representing a weight matrix, and such that the weight ma...
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JP2023162924A |
To realize a reservoir computing device at low cost.The reservoir computing device includes: an optical medium which propagates in different times according to frequencies; generation means for generating plural continuous lights with di...
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JP2023546821A |
A method and circuit for performing vector-matrix multiplication involves converting an input vector of binary encoded values into an analog signal using a 1-bit DAC and sequentially performing vector-matrix multiplication operations per...
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JP7371235B2 |
Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural netw...
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JP7365999B2 |
An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural n...
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JP2023543971A |
Implement analog memory-based neural network pipeline processing with all-local storage. An array of inputs is received by the first synaptic array of the hidden layer from the previous layer during a feed forward operation. The array of...
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JP7365339B2 |
A method of assessing odors, comprises providing an electronic nose that extracts measurements from odors, from which measurements at least n chemical descriptors are extracted where n is greater than unity, and typically around 18. The ...
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JP2023153778A |
To provide an improved decoding system and physical layout for an analog neural memory system which uses a non-volatile memory cell.An analog neural memory system includes a plurality of vector matrix multiplication arrays, a plurality o...
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JP7364244B2 |
A multiplier has a pair of charge reservoirs. The pair of charge reservoirs are connected in series. A first charge movement device induces charge movement to or from the pair of charge reservoirs at a same rate. A second charge movement...
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JP7364586B2 |
A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit inc...
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JP7359935B2 |
Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array ...
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JP7358100B2 |
A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low powe...
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JP7357079B2 |
A computer implemented method includes updating weight values associated with a plurality of analog synapses in a cross-bar array that implements an artificial neural network by sending a pulse sequence to the analog synapses. Each analo...
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JP7356393B2 |
A first voltage application circuit applies a first voltage determined to have a first voltage value to a first wiring connected to an asymmetrical memory cell. A second voltage application circuit applies a second voltage determined to ...
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JP2023139013A |
To provide an analog neural memory system and method that has an input block and an output block which are configurable and a physical layout and that uses a nonvolatile memory cell.In a vector matrix multiplication (VMM) system 3400, an...
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JP2023137770A |
To improve inference performance of artificial intelligence by increasing the number of neurons in an optical neural network device.A speckle generation circuit used in an optical neural network device 1 comprises: a phase modulator 113 ...
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JP2023539845A |
Numerous embodiments of analog neural memory systems are disclosed that enable simultaneous write and verify operations. In some embodiments, simultaneous operations occur between different banks of memory. In other embodiments, simultan...
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JP7345859B2 |
It is described a mathematical solving circuit (100) comprising: a crosspoint matrix (MG) including a plurality of row conductors (Li), a plurality of column conductors (Cj) and a plurality of analog resistive memories (Gij), each connec...
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JP7346579B2 |
Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificia...
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JP7346510B2 |
A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a funct...
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