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JP6817922B2 |
To provide an arithmetic device capable of reducing energy consumption.A calculation device in an embodiment includes: a first magnetic part; a first reading part; a storage part; and a calculation part. The first reading part is configu...
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JP6818116B1 |
To provide an electronic device using a crossbar array capable of high-speed processing and highly reliable processing. An arithmetic processing unit 100 of the present invention includes a crossbar array 110, a row selection / drive cir...
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JP2021002133A |
To improve the accuracy of operation in an analog circuit performing product sum operation.An arithmetic unit has first and second arithmetic circuit parts. Product sum signals output from a plurality of output lines of the first arithme...
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JP6806597B2 |
The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is configured to generate a first current corresponding to first analog data and to ...
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JP6805984B2 |
A image recognition system includes a first convolution layer, a pooling layer, a second convolution layer, a crossbar circuit having a plurality of input lines, at least one output line intersecting with the input lines, and a plurality...
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JP6800460B2 |
To correct, revise accurately and properly, and improve arithmetic means of all industries such as measurement or control, by using some in a formula group of N or a combination thereof.N-operators such as standing, pole, sky Po,[ which ...
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JP6794891B2 |
A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion am...
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JP6789576B2 |
A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operat...
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JP6782193B2 |
An information processing device has a digital-to-pulse converter which outputs a pulse signal including a pulse having a pulse length in accordance with a digital input signal, and a selective oscillator which performs an oscillation op...
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JP6773521B2 |
A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor ...
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JP6773621B2 |
According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-si...
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JP6773239B2 |
A product-sum operation device includes a product operator and a sum operator. The product operator includes a plurality of variable-input product operation elements and a plurality of fixed-input product operation elements. Each of the ...
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JP2020166793A |
To provide a semiconductor device and a method for configuring a neural network that implement a neural network structure without relying on software.A semiconductor device 10 can construct a neural network at least composed of a synapse...
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JP2020160888A |
To provide a computing device, etc., with which it is possible to realize efficient and high-speed computing.The computing device comprises a plurality of input lines and one or more product-sum computing devices. An electric signal corr...
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JP2020160145A |
To provide a signal waveform technique such that timbre is wide in width, control is easy, and computational complexity is small.There is provided a signal waveform synthesis device comprising a time varying neural network having a hiera...
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JP2020160887A |
To provide a computing device, etc., with which it is possible to simplify a circuit configuration and realize a high-speed arithmetic processing.The computing device comprises a plurality of input line pairs and one or more product-sum ...
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JP6756287B2 |
A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage a...
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JP6747610B2 |
A product-sum operation device includes a product operator, a sum operator, and a malfunction determiner. The product operator includes a plurality of product operation elements (10AA) to (10AC), and each of the plurality of product oper...
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JP2020126426A |
To provide a computation device and a product-sum operation system in which a circuit configuration can be simplified and the power consumption of product-sum operation can be reduced in an analog circuit that performs a product-sum oper...
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JP6744375B2 |
The present relates to invention deals with an execution unit configured to execute a computer program instruction to generate random numbers based on a predetermined probability distribution. The execution unit comprises a hardware pseu...
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JP6732880B2 |
The device for processing data comprises a set of processing nodes and connections between the nodes. Each connection is configured to transmit, to a receiver node, events delivered by an emitter node. Each node is arranged to vary a res...
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JP2020109715A |
To provide an electronic device for being used in an artificial neuron network.An electronic device 100 includes an artificial neuron array (ANA) 111, a row decoder 112, a column decoder 113, an input circuit 114, an output circuit 115, ...
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JPWO2018234919A1 |
Provided is a semiconductor device capable of efficiently performing image recognition using a neural network. The semiconductor device includes a shift register group, a D / A converter, and a product-sum calculation circuit. The produc...
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JP6724870B2 |
A method for training an artificial neural network circuit is provided. The artificial neural network circuit includes a crossbar circuit that has a plurality of input bars, a plurality of output bars crossing the plurality of input bars...
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JP6724863B2 |
A convolutional neural network includes: convolution layers and a merging layer. At least one convolution layer includes a crossbar circuit having input bars, output bars and weight assignment elements that assign weights to input signal...
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JP6724869B2 |
A method for adjusting output level of a neuron in a multilayer neural network is provided. The multilayer neural network includes a memristor and an analog processing circuit, causing transmission of the signals between the neurons and ...
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JP6721136B2 |
A multiply and accumulate calculation device (1) includes a multiple calculation unit (10) and a accumulate calculation unit (11). The multiple calculation unit (10) includes a plurality of multiple calculation elements (10AA, 10AB), whi...
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JP6715644B2 |
A semiconductor device including cells arranged in a matrix with m rows and n columns, where each of m and n is an integer of 2 or more, in which the cells retain first data with m rows and n columns, the cells input second data with m r...
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JP2020098994A |
To provide a polynomial division circuit suitable for Euclidean decoding.A division circuit 50 for obtaining a greatest common divisor polynomial of a syndrome polynomial and xwhere the number of continuous roots of the generator polynom...
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JP6708146B2 |
A neural network circuit is provided. The neural network circuit includes a memory device including memristors connected in a matrix, a controller arranged to control a voltage application device to perform writing, deleting and reading ...
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JP2020080159A |
To provide an electronic apparatus that is used for an artificial neuron network.An electronic apparatus 100 has a first circuit 10[1, m], a second circuit 11[n], and first to sixth wires. The first circuit has a first transistor M1, a s...
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JPWO2018186390A1 |
Input unit 1 to which a voltage is applied, current output unit 3 that outputs a high level current or low level current according to the voltage applied to the input unit 1, and high level current or low level current from the current o...
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JP6678797B2 |
The power consumption of an analog arithmetic circuit is reduced. The analog arithmetic circuit includes a plurality of first circuits. An output terminal of the k-th (k is a natural number) first circuit is connected to an input termina...
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JP6674838B2 |
An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capa...
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JP6668282B2 |
According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charg...
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JP2020037233A |
To provide a technique for efficiently improving a determination rate of a return determination model with necessary minimum learning data during applying machine learning to return determination of a device provided with a human detecti...
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JP6647429B2 |
The present invention concerns a method of programming an analogue electronic neural network (1) comprising a plurality of layers of somas (3). Any two consecutive layers of somas (3) are connected by a matrix of synapses (5). The method...
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JP2020021356A |
To provide a semiconductor device having high degree of integration and achieving power saving.A semiconductor device comprises: an input unit 1 which applies an input voltage; a bistable circuit unit 3 in which a transition probability ...
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JP6636529B2 |
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JP6637602B2 |
Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN d...
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JP2020009123A |
To provide a product-sum operation device, a product-sum operation circuit, and a product-sum operation method capable of dispersing signal output timings.A product-sum operation device includes: a comparison unit that compares a voltage...
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JP2020009317A |
To minimize power consumption.A signal processing circuit disclosed herein comprises: a plurality of first circuits, each comprising a first duration signal output circuit configured to output a first duration signal representing a durat...
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JP2020500363A |
Learning algorithms for oscillating memory neural morphological circuits are described. In an embodiment, the neuromorphological circuit learning network comprises a plurality of neuromorphological circuit nodes, each containing a cognit...
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JP2019537792A |
The concept of memory learning for neuromorphological circuits is explained. In one example, the neuromorphological circuit is electrically coupled to a first oscillation-based neuron that produces the first oscillation signal, a diode t...
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JP6623947B2 |
Arithmetic circuits calculate d−1 energy values (hi2 to hid) indicating energies generated by 2-body to d-body coupling on the basis of a plurality of weight values indicating strength of 2-body to d-body coupling of 2 to d neurons inc...
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JP2019197518A |
To provide an ultra-high-speed general-purpose computing device capable of uniformly performing computation in scales ranging from elementary particles to the universe at infinite speed regardless of whether an object is living or inanim...
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JP2019179499A |
To provide a semiconductor device and a product-sum computation device which further reduce a mounting area per synapse, and thereby enable integration with higher density.A semiconductor device comprises: a plurality of synapses in whic...
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JP6591548B2 |
A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF...
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JP2019168851A |
To provide an arithmetic processing apparatus and an arithmetic processing method capable of being configured to reduce a circuit area and to speed up arithmetic processing.The arithmetic processing apparatus according to an embodiment i...
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JP2019161068A |
To provide a novel three-terminal analog operation element for implementing large-scaled synapse calculation for neuro-morphic learning.An MOSFET element 10 having a laminated structure of amorphous oxides is an MOS capacitor structure c...
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