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WO/2023/206749A1 |
A calibration control circuit (10), an electronic device, and a calibration control method. The calibration control circuit (10) comprises an off-chip calibration module (11) and a mode switching module (13), and the off-chip calibration...
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WO/2023/212429A1 |
A storage device reclassification system includes a storage device reclassification subsystem coupled to a storage device that has a NAND storage subsystem and that is configured to perform first storage operations associated with a firs...
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WO/2023/212117A1 |
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells.The control circuit is configured to: acquire a first set of read levels on a wordline of a first block o...
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WO/2023/210382A1 |
In the present invention, a processor acquires a first signal based on a first result of the servo pattern being read by a first servo read element while the first servo read element is located on the reference area of magnetic tape, acq...
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WO/2023/207806A1 |
A shift register, a gate driving circuit and a display apparatus. The shift register comprises a first control module (10), a first output module (20), a second output module (30), a second control module (40), a third control module (50...
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WO/2023/207543A1 |
A media content publishing method and apparatus, and a device, a storage medium and a program product. The method comprises: in response to a publishing page display operation acting on a photographic page, switching the current display ...
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WO/2023/206752A1 |
Disclosed in the embodiments of the present disclosure are a test method and test system for a memory. The method comprises: providing a memory, wherein the memory at least comprises a plurality of first storage units and a plurality of ...
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WO/2023/208571A1 |
A data storage medium (2) comprising a stacked plurality of layers (9), each layer composed of a layer material selected from a group comprising at least two different dielectric materials, adjacent layers being formed of different mater...
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WO/2023/206152A1 |
An anti-fuse memory, for use in increasing a read success rate of the anti-fuse memory. The anti-fuse memory comprises a storage unit, a bit line, a word line, and a write line. The storage unit comprises an active region, and a selectio...
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WO/2023/212568A1 |
An integrated circuit (IC) may include a memory device and a circuit coupled with the memory device. The circuit may precondition the memory device to sustain oscillations, initiate first oscillations in a first loop that includes the me...
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WO/2023/210643A1 |
[Problem] To provide a hardware accelerator processor for full-text search. [Solution] Provided is a full-text search processor comprising: a character storage element in which text data to be searched is temporarily stored such that eac...
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WO/2023/209485A1 |
Provided is a semiconductor device having a small circuit size and reduced power consumption. This semiconductor device includes first to fifth circuits. Each of the first to fourth circuits has first and second cells, a sixth circuit, f...
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WO/2023/207380A1 |
Embodiments of the present application relate to a calibration circuit and method and a related device. The circuit is electrically connected to a ZQ port, and a reference resistor corresponding to the ZQ port is grounded; the circuit co...
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WO/2023/209491A1 |
Provided is a semiconductor device that has a novel structure. The present invention has: a base die that has a clock signal generation circuit and a first synchronization circuit provided thereto; and a plurality of dies that are layere...
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WO/2023/210161A1 |
The present invention inhibits a reduction in the life of a nonvolatile memory in which write processing is performed again when a write operation fails. A memory cell is interposed between a pair of signal lines. A write control circu...
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WO/2023/210388A1 |
The present technology is an information processing device, a method, and a program that facilitate understanding respective parts in a musical piece that respective players are in charge of. The information processing device includes a ...
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WO/2023/208088A1 |
Embodiments of the present application relate to the technical field of electronics. Disclosed are a storage chip, a storage apparatus and an electronic device. The storage chip comprises a plurality of first storage units, and each firs...
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WO/2023/211613A1 |
Systems and methods for adaptive data encoding for memory systems are disclosed. In one aspect, a memory bus replaces a data bus inversion encoding technique with a more flexible encoding scheme which periodically calculates cluster cent...
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WO/2023/208719A1 |
The invention relates to an energy efficient non-volatile cryogenic memory (SUPERTRACK) which comprises - a ferrimagnetic, ferromagnetic or synthetic antiferromagnetic racetrack (RT); and a superconducting shift element in proximity to t...
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WO/2023/209973A1 |
The present invention comprises a plurality of voltage generation circuits (1, 2, 3) which are provided in an environment to be irradiated with neutron rays and which are connected in parallel. Each of the voltage generation circuits com...
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WO/2023/206657A1 |
A test circuit (400), a test method, and a memory. The test circuit (400) comprises: a first integrating circuit (401) used for receiving a first test signal (Test1) and configured to integrate the first test signal (Test1) to output a f...
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WO/2023/211511A1 |
Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a ...
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WO/2023/211532A1 |
Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first l...
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WO/2023/206632A1 |
Disclosed in the embodiments of the present disclosure are a detection circuit for a storage array, a detection method of the detection circuit, and a memory. The detection circuit for a storage array comprises: at least one storage arra...
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WO/2023/206634A1 |
Provided in the embodiments of the present disclosure are a calibration control circuit, an electronic device and a calibration control method. The calibration control circuit comprises: an off-chip calibration module, configured to rece...
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WO/2023/206751A1 |
Embodiments of the present invention provide a calibration control circuit, an electronic device, and a calibration control method. The calibration control circuit comprises: a process module configured to, in a first test mode, perform ...
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WO/2023/204889A1 |
Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap posit...
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WO/2023/204111A1 |
A plurality of SRAM cells (C1) are commonly connected to both a write bitline (WBL, WBLB) extending in a Y-direction and a local read bitline (RBL) extending in the Y-direction. A local amplifier (B1) connected to the local read bitline ...
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WO/2023/204348A1 |
The present invention relates to a smartphone recorder. The smartphone recorder according to an embodiment of the present invention comprises: a case body comprising a front cover attachable to/detachable from the rear surface of a smart...
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WO/2023/203790A1 |
A memory system (1), which is an example of a storage device according to one embodiment of the present disclosure, comprises a magnetoresistive element (120) that has a magnetization direction variable between a first state and a second...
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WO/2023/205322A1 |
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of ...
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WO/2023/204237A1 |
A magnetic recording medium manufacturing method according to the present invention is a method for manufacturing a magnetic recording medium comprising a substrate, an underlayer, and a perpendicular magnetic layer having an L10 structu...
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WO/2023/203431A1 |
Provided is a semiconductor device that has a small circuit scale and in which power consumption is reduced. The semiconductor device has first to fourth cells, first and second circuits, and first to fourth current generation circuits. ...
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WO/2023/202061A1 |
A nano memory for ultra-high-density data storage, and a preparation method therefor. Donor and acceptor groups are reasonably introduced into an amphiphilic block copolymer, micelles are formed by means of self-assembly to serve as memo...
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WO/2023/203435A1 |
Provided is a semiconductor device having a novel configuration. The semiconductor device includes: a first element layer including a control unit; and a second element layer provided as stacked on the first element layer. The second ele...
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WO/2023/202166A1 |
A bit line reading circuit (201), a memory (1) and an electronic device. In the bit line reading circuit (201), a bit line (BL) is connected to a ferroelectric memory cell (101), and the ferroelectric memory cell (101) comprises n ferroe...
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WO/2023/203512A1 |
Systems and methods for automatically gating a data strobe during a read operation by the DRAM are disclosed. The method includes detecting, and automatically opening the gate when the DQS signal is driven. A system for automatically gat...
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WO/2023/201883A1 |
A memory failure test method, a memory failure test apparatus, a computer-readable storage medium, and an electronic device, relating to the technical field of integrated circuits. The memory failure test method comprises: executing a da...
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WO/2023/200468A1 |
A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, sc...
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WO/2023/197399A1 |
Disclosed are a memory testing method and apparatus, and a memory system. The method comprises: executing a write operation and a read operation on a memory unit in a noise environment, wherein the write operation comprises writing test ...
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WO/2023/199182A1 |
Provided is a novel semiconductor device. The semiconductor device comprises a first cache, a second cache, a cache controller, and cores, wherein the cache controller has a function that causes data for performing program processing to ...
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WO/2023/197678A1 |
Disclosed in the embodiments of the present application are an information recording method and apparatus, and an electronic device and a storage medium. The method comprises: during a running process of a playing program, in response to...
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WO/2023/200733A1 |
Examples of a load beam are provided. The load beam includes a base portion with an opening at a distal end. The opening is configured to receive a heat assisted magnetic recording (HAMR) head slider extending therethrough. The load beam...
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WO/2023/200767A1 |
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold sw...
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WO/2023/198189A1 |
Disclosed are a memory error prediction method and apparatus, and a device, which relate to the field of computers. After memory error data is acquired, on the basis of spatial-temporal information that reflects a memory error, and a phy...
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WO/2023/199796A1 |
Provided is an electronic device that enables a reduction in dust or the like that adheres to a ventilation region of a heat-generating component or a heat-dissipating component. An electronic device (10) has: a power supply unit (40); a...
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WO/2023/197767A1 |
A ferroelectric memory (100). A first storage unit in the ferroelectric memory (100) comprises a transistor and a plurality of capacitors; first electrode plates of the plurality of capacitors are connected to a drain of the transistor; ...
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WO/2023/199474A1 |
This memory device comprises a page made of a plurality of memory cells arranged in columns, in plan view, on a substrate, wherein, during a page erase operation, voltages to be applied to a first impurity layer, a second impurity layer,...
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WO/2023/197389A1 |
A neuron device (10) based on a magnetic tunnel junction, and a neural network apparatus. The neuron device (10) based on a magnetic tunnel junction comprises: a synthetic antiferromagnetic structure layer (111), wherein a bottom electro...
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WO/2023/197774A1 |
A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of ...
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