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WO/2023/231263A1 |
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising: a refresh control circuit, a repetitive command processing circuit and an address generator. The refresh control circuit is used ...
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WO/2023/231295A1 |
A refresh address generation circuit and method, and a memory and an electronic device. The refresh address generation circuit comprises a refresh control circuit (100) and an address generator (200), wherein the refresh control circuit ...
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WO/2023/235115A1 |
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate ind...
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WO/2023/235339A1 |
Systems, devices, and methods for a laser diode assembly (102) including: a laser diode (120) configured to emit a laser beam (200); and a housing (124) configured to receive at least a portion of the laser diode (120), where the housing...
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WO/2023/231177A1 |
The present disclosure provides a receiving circuit and a memory. The receiving circuit comprises: an input buffer, configured to receive a first input signal and a second input signal and compare the first input signal with the second i...
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WO/2023/232749A1 |
A system for the electrochemical synthesis of polymers, comprising: a. one or more reaction chambers comprising an inlet, an outlet, and a plurality of reaction sites comprising one or more individually addressable electrodes, b. a plura...
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WO/2023/231090A1 |
A termination impedance parameter generation method and test system. The method comprises: when a first operation instruction is received, writing a plurality of preset control words into a first data queue in a data buffer (S201), where...
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WO/2023/235157A1 |
A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to a...
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WO/2023/231273A1 |
Provided in the present disclosure are a test method, test equipment and a computer storage medium. The method comprises: determining an initial clock signal; generating a target clock signal on the basis of the initial clock signal; acq...
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WO/2023/231223A1 |
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising a refresh control circuit and an address generator. The refresh control circuit sequentially receives a plurality of first refresh...
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WO/2023/235037A1 |
The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses with...
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WO/2023/231276A1 |
The present invention relates to the field of very-large-scale integrated circuit testability design. Disclosed is a chiplet test circuit based on flexible configurable modules (FCMs). A circuit core structure is located in an intermedia...
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WO/2023/230835A1 |
A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit (Isc...
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WO/2023/235055A1 |
Computer memory systems employing localized generation of a global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods. The memory system includes one or more memory b...
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WO/2023/226112A1 |
Provided in the embodiments of the present disclosure are a refresh control circuit, a memory, and a refresh control method. The refresh control circuit comprises: a processing module which is configured to receive a refresh command sign...
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WO/2023/226066A1 |
A GOA (Gate Driver On Array) circuit and a display panel. The present invention employs a first GOA unit (sGOA) of each stage of GOA module to realize upward and downward signal transmission, so as to reduce the number of thin film trans...
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WO/2023/229816A1 |
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memor...
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WO/2023/226417A1 |
A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial...
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WO/2023/225847A1 |
A shift register unit, comprising: a sensing control circuit (1), connected to a sensing signal input end (INPUT2), a random signal input end (OE), and a sensing control node (H), and configured to write a signal provided by the sensing ...
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WO/2023/229815A1 |
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets th...
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WO/2023/229807A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge p...
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WO/2023/229369A1 |
A video storage apparatus according to an embodiment of the present invention comprises: a spare power source that supplies auxiliary power; a main board that selects, from videos transmitted over a network, a video to store; a video sto...
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WO/2023/229009A1 |
An aspect of the present disclosure provides a grinding liquid composition that can reduce residue of silica on a substrate surface after grinding is performed, while maintaining a grinding rate. One aspect of the present disclosure pe...
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WO/2023/225704A1 |
The present invention relates generally to the field of digital content, and more particularly to an improved system and methods for producing, mixing, and recording content. In particular, the system may include a plurality of input cha...
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WO/2023/226060A1 |
Provided in the present application is a counter circuit, comprising an addition module, a subtraction module and a plurality of control modules. The addition module comprises a plurality of stages of counting modules for corresponding b...
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WO/2023/229840A1 |
A double data rate (DDR) physical (PHY) provides an interface between a memory controller and a dynamic random-access memory (DRAM). The DDR PHY includes a first set of core logic configured to convert data between a single data rate and...
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WO/2023/229683A1 |
Techniques are described for managing video editing projects using single bundled video files. A single bundled video file is a new type of file that is in a video container format and that can be used to store and re-create a video edit...
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WO/2023/227027A1 |
The present disclosure relates to the technical field of display and provides a shift register and a drive circuit and method therefor, a display panel, and a device. The shift register comprises an input unit, a first control unit, an o...
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WO/2023/229524A1 |
A computing system is provided which includes a client computing device including a processor. The processor is configured to execute a client program to display a first video published by a first user on a video server platform, to a se...
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WO/2023/225946A1 |
Provided in the embodiments of the present disclosure are a shift register unit, a driving control circuit, a display apparatus and a driving method. The shift register unit comprises: an input circuit, which is configured to provide an ...
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WO/2023/229808A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corres...
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WO/2023/226540A1 |
Provided in the present invention are a magnetic random access memory device and a manufacturing method therefor. The device comprises magnetic thin film structure bodies, and an electrode capable of applying voltage to a magnetic thin f...
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WO/2023/228544A1 |
A compound according to one embodiment of the present disclosure is represented by formula (1). In formula (1), R1 to R4 each independently is an optionally substituted hydrocarbon group.
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WO/2023/226453A1 |
Disclosed in the present application are a silicon-wafer system and a repair method therefor, and an electronic device. By means of an optical interconnection layer which is additionally provided between a processor layer and a memory la...
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WO/2023/226062A1 |
Provided in the present application is a counter circuit. The counter circuit comprises multiple stages of counting modules corresponding to binary digits. Each stage of counting module is used for obtaining a carry signal and a present-...
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WO/2023/226061A1 |
Embodiments of the present disclosure provide an instruction test method and device, a test platform, and a readable storage medium, and relate to the technical field of semiconductors. The method comprises: when a target instruction to ...
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WO/2023/229814A1 |
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the...
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WO/2023/226128A1 |
Disclosed in the embodiments of the present disclosure are a delay adjustment method, a storage chip architecture and a semiconductor memory. The method comprises: measuring a first delay of a first signal path; on the basis of the first...
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WO/2023/228553A1 |
In the present invention, a reference potential used for detecting data stored in memory cells is optimized in accordance with the positions where the memory cells are arranged. This nonvolatile storage device includes memory cells and r...
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WO/2023/228869A1 |
The standard for computing storage capacity in modern computing is a bit, and the number of transistors (elements) that are to be nodes, namely, the number of bits is a quantitative unit of modern information communication. In contrast, ...
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WO/2023/226235A1 |
Provided in the embodiments of the present disclosure are a magnetic random access memory and a read-write method therefor, and a storage apparatus. The magnetic random access memory comprises a storage array, a write circuit and a write...
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WO/2023/221391A1 |
Embodiments of the present disclosure provide an anti-fuse circuit, comprising: an anti-fuse unit; a programming circuit, used to program the anti-fuse unit according to a programming signal; and a verification unit, comprising a first i...
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WO/2023/223127A1 |
A semiconductor device having a high storage density is applied in the present invention. This semiconductor device has a first layer and a first insulating material. The first layer has a first oxide semiconductor, first to ninth conduc...
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WO/2023/221390A1 |
Embodiments of the present disclosure provide an anti-fuse circuit, comprising: an anti-fuse unit; a reading unit for reading the anti-fuse unit to obtain a data signal; a verification control unit disposed between an input end of the re...
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WO/2023/224095A1 |
This fluorine-containing ether compound is represented by the following formula. R1-R2-CH2-R3[-CH2-R4-CH2-R3]x-CH2-R5-R6 (where R1 and R6 are organic groups having 1-50 carbon atoms, R2 is formula (2-1) or (2-2), R5 is formula (2-3) or (...
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WO/2023/223673A1 |
An optical recording medium 100 in one aspect of the present disclosure comprises a recording layer 10 and a dielectric layer 20 positioned on the recording layer 10 and including a porous organic structure. The method for recording info...
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WO/2023/223674A1 |
A recording medium 100 according to an aspect of the present disclosure comprises a recording layer 10 containing a polymer P. The polymer P contains a group G having nonlinear light absorption properties and has a glass transition tempe...
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WO/2023/221252A1 |
Disclosed in the present invention is a pulse voltage generation apparatus having an adjustable pulse width. The apparatus comprises: a switch control circuit, which is used for generating a control signal; a clock generation circuit, wh...
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WO/2023/221021A1 |
Memory systems, memory devices, and methods for read reference voltage management are provided. The memory system may include a memory device and a memory controller. The memory device may include one or more memory cells associated with...
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WO/2023/222458A1 |
The invention relates to improving the quality of an audio and/or video recording which is made by means of a mobile terminal (10), wherein the recording is started by means of a start activity to be manually performed on the mobile term...
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