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WO/2024/064075A1 |
Methods, systems, and media for providing automated assistance during a video recording session are provided. In some embodiments, the method comprises: receiving, at a first user device, user input to initiate a video recording session,...
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WO/2024/063794A1 |
Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a ...
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WO/2024/060315A1 |
Provided in the present disclosure are a built-in self-test method, a built-in self-test apparatus and a semiconductor memory. The method comprises: acquiring temperature data of a storage unit, and according to the temperature data, adj...
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WO/2024/060059A1 |
A memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of ...
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WO/2024/060611A1 |
A method of realizing a content-addressable memory (CAM) based on field effect transistors having bipolar characteristics. By inserting a storage layer between a gate dielectric layer and a control gate of a field effect transistor havin...
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WO/2024/063793A1 |
Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling si...
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WO/2024/060323A1 |
Embodiments of the present disclosure provide a counting circuit, a semiconductor memory, and a counting method. The counting circuit comprises a first decoding module and a first counting module, and the first decoding module is connect...
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WO/2024/060365A1 |
Provided in the embodiments of the present disclosure are a word-line driver, and a storage apparatus. The word-line driver comprises: a first holding transistor and a second holding transistor; an active area, comprising a main body por...
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WO/2024/063792A1 |
Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory ce...
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WO/2024/060317A1 |
Embodiments of the present disclosure provide a command decoding circuit and a method thereof, and a semiconductor memory. The command decoding circuit comprises: a clock processing module, which is configured to receive an initial clock...
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WO/2024/060378A1 |
The present disclosure relates to the technical field of memories. Provided are a dynamic random access memory test method and apparatus. A dynamic random access memory comprises a substrate and a plurality of storage units, wherein each...
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WO/2024/060316A1 |
A built-in self-test method and device. The built-in self-test method comprises: acquiring a first initial address of a storage region (110) of data to be written, and masking at least one bit address of the first initial address, so as ...
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WO/2024/061005A1 |
A read processing method and apparatus for an audio and video buffer. The data read-write mode of the audio and video buffer is improved. Consumer modules create respective handles for reading data. Using a read handle as a unique identi...
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WO/2024/062978A1 |
A magnetoresistive element according to one embodiment of the present disclosure comprises a multilayer structure, a memory layer disposed on the multilayer structure and changeable in magnetization direction, a nonmagnetic layer dispose...
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WO/2024/063315A1 |
Disclosed is a three-dimensional memory having a dual junction structure. According to an embodiment, the three-dimensional memory may comprise: gate electrodes spaced apart and stacked in a vertical direction while extending in the hori...
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WO/2024/062539A1 |
This memory device, in which in a plan view on a substrate, a page is formed by a plurality of memory cells arranged in the row direction and a plurality of the pages are arranged in the column direction, is characterized in that: the me...
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WO/2024/060478A1 |
The embodiments of the present disclosure disclose a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit comprises a first signal path and a second signal path. The first signal path is configured to ...
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WO/2024/060325A1 |
A decoding circuit (10), a decoding method and a semiconductor memory. The decoding circuit (10) comprises a decoding module (11) and a register module (12). The decoding module (11) is configured to perform decoding processing on an ini...
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WO/2024/060219A1 |
In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through th...
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WO/2024/060555A1 |
The application discloses a chip test method and apparatus, a chip and a computer readable storage medium. The method comprises: a main controller sends a test instruction to each sub-controller in a storage built-in self-test circuit; a...
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WO/2024/058321A1 |
The present invention relates to a memory device including memory cells in which data is stored by the operation of word lines and bit lines, the memory device comprising: a first switch which has one end connected to a bit line connecte...
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WO/2024/055358A1 |
A data processing method, an electronic device, and a computer readable storage apparatus. The method comprises: determining a target layer corresponding to a target storage unit; and operating a storage unit in a non-target layer to imp...
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WO/2024/055832A1 |
Provided in the present disclosure are a non-volatile memory and an erasing method therefor, and a computer system. The non-volatile memory comprises a first area, which needs to be erased, and a second area, which does not need to be er...
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WO/2024/059428A1 |
A device includes a memory configured to store data corresponding to a media stream including video recorded at a first frame rate and multiple audio segments includes the multiple audio segments include one or more first audio segments ...
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WO/2024/058909A1 |
Technology is disclosed for programmatically determining, for a segment of a meeting recording, a user-specific adaptive playback speed, and generating a time-stretched segment playable at the adaptive playback speed. The adaptive playba...
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WO/2024/055685A1 |
The present application relates to the technical field of semiconductor chips, and provides a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, which improve the anti-interference capability of capac...
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WO/2024/055611A1 |
The present application relates to the technical field of firmware emulation, and in particular to a fault site backtracking method based on firmware emulation, and a device and a readable storage medium. The method comprises: upon recei...
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WO/2024/055484A1 |
The embodiments of the present disclosure provide a programmable storage array, a programming method and a semiconductor memory. The programmable storage array comprises a plurality of storage units. Each storage unit comprises a first t...
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WO/2024/057519A1 |
In the present invention, a first string includes a first memory cell transistor, one end of the first string being connected to a first wire, the other end being connected to a second wire. A second string includes a second memory cell ...
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WO/2024/057114A1 |
A 3D compute-in-memory accelerator system (100) and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores (102), each in-memory core including multiple...
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WO/2024/055373A1 |
Embodiments of the present disclosure relate to the technical field of semiconductors, and provide a voltage regulating circuit and a memory thereof. The voltage regulating circuit comprises: a reference voltage generation module, config...
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WO/2024/057947A1 |
Provided are a magnetic recording medium and a magnetic recording cartridge. An average thickness of the magnetic recording medium tT is tT ≦ 5.3 μm, and a width of the magnetic recording medium is stabilized in 24 minutes or less a t...
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WO/2024/055655A1 |
Disclosed in the present invention is a memory read-write verification method, comprising: firstly, performing margin verification on all IOs of a memory according to input data, and according to a verification result, acquiring read-out...
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WO/2024/055394A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system, and a storage apparatus. The data receiving circuit comprises: a decision feedback equalization module, which is configured to e...
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WO/2024/058877A1 |
A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data regist...
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WO/2024/057941A1 |
A semiconductor memory device (1) comprises: a first pull-down N-channel MOS transistor (21) having a drain connected to a word line (20), a source connected to a ground line, and a gate connected to a first node (91); a first series-con...
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WO/2024/057529A1 |
A semiconductor device according to an embodiment includes: an operational amplifier that has a first input terminal, a second input terminal, and an output terminal, and that outputs a first voltage from the output terminal; a first res...
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WO/2024/058042A1 |
This recording device records data to a non-volatile storage device in a recording mode in which the lowest recording speed is guaranteed. The non-volatile storage device has a memory that performs data recording compliant with NVMe stan...
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WO/2024/054303A1 |
Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory a...
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WO/2024/050926A1 |
Embodiments of the present disclosure provide a data processing structure, a semiconductor structure and a memory. The data processing structure comprises a data sampling module, the data sampling module comprises a logic module and a co...
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WO/2024/053014A1 |
This memory device having, on a substrate in a plan view, a plurality of pages which are each formed by a plurality of memory cells arrayed in the row direction and which are arrayed in the column direction is characterized in that: the ...
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WO/2024/051658A1 |
A shift register unit and a display panel. The shift register unit comprises: a first control circuit (10), a second control circuit (20), a third control circuit (30), and an output circuit (40), wherein the first control circuit (10) i...
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WO/2024/054888A1 |
The subject technology receives frames of a source media content. The subject technology detects from the frames of the source media content, a first gesture indicating a cut point at a particular frame of the source media content, the c...
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WO/2024/050905A1 |
Embodiments of the present disclosure provide a mode register setting code generation circuit and method, a circuit and method for setting a mode register, and a memory. The mode register setting code generation circuit comprises: at lea...
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WO/2024/054280A1 |
The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determine...
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WO/2024/053740A1 |
Provided is a glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproducing device that is an amorphous glass that has a B2O3 content of 0.10-2.00 mol% inclusive, a Na2O content of 1...
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WO/2024/053176A1 |
The present invention provides a sputtering target which enables a magnetic layer of a magnetic recording medium to maintain high coercivity, while being capable of improving magnetic separation between magnetic particles. This sputterin...
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WO/2024/053056A1 |
Provided is glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproduction device, said glass being amorphous glass with a B2O3 content of 0.10-2.00 mol%, a Na2O content of 1.00-6.00...
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WO/2024/053015A1 |
The present invention provides a memory device in which a page is formed from a plurality of memory cells arranged in a row direction and a plurality of pages are arranged in a column direction on a substrate in a plan view. The memory c...
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WO/2024/054317A1 |
Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory I...
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