Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2020065084
Kind Code:
A
Abstract:
To provide a method for manufacturing a trench gate type semiconductor device having a dummy trench MOS cell and having a low market failure rate.SOLUTION: First, on a front surface of an ntype semiconductor substrate 1 are formed a trench MOS cell having a gate electrode 8 extending in a depth direction of a device and a dummy trench MOS cell having a dummy gate electrode 18 extending in the depth direction of the device. Next, an emitter electrode 9 and a screening pad DG are formed on the front surface of the ntype semiconductor substrate 1. The dummy gate electrode 18 is connected to the screening pad DG. Next, a predetermined voltage is applied between the emitter electrode 9 and the screening pad DG to perform screening on a dummy gate insulating film 17. Next, a product is completed by short-circuiting the emitter electrode 9 and the screening pad DG with a plating film 13 that covers the emitter electrode 9 and the screening pad DG.SELECTED DRAWING: Figure 1
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Inventors:
MOMOTA SEIJI
ABE KAZU
KONO KENJI
TANABE HIROMITSU
ABE KAZU
KONO KENJI
TANABE HIROMITSU
Application Number:
JP2020007912A
Publication Date:
April 23, 2020
Filing Date:
January 21, 2020
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD
DENSO CORP
DENSO CORP
International Classes:
H01L21/336; H01L21/02; H01L21/66; H01L29/739; H01L29/78
Domestic Patent References:
| JP2014053552A | 2014-03-20 | |||
| JP2013183143A | 2013-09-12 | |||
| JP2010050211A | 2010-03-04 | |||
| JP2007013034A | 2007-01-18 | |||
| JP2004500720A | 2004-01-08 |
Attorney, Agent or Firm:
Akinori Sakai