Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP3577419
Kind Code:
B2
Abstract:
A semiconductor device has excellent bonding strength of bumps (38) with their respective protruded electrodes (32) and has high reliability. A wiring pattern (28) to be connected to an electrode (22) of a semiconductor chip (20) is formed on an insulating film (23) formed on the semiconductor chip (20) in which the electrode (20) is formed. Protruded electrodes (32) are formed on the wiring pattern (28). The wiring pattern (28) is covered with a protective film (36), and a bump (38) for external connection is formed on the end portion of each of the protruded electrodes (32) exposed from the protective film (36). The bump (38) is formed in such a manner that the bump is bonded to at least the entire end face of each of the protruded electrodes (32).
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Inventors:
Shoichi Kobayashi
Naoyuki Koizumi
Hajime Iizuka
Osamu Uehara
Naoyuki Koizumi
Hajime Iizuka
Osamu Uehara
Application Number:
JP35922998A
Publication Date:
October 13, 2004
Filing Date:
December 17, 1998
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L21/60; H01L23/12; H01L23/485; (IPC1-7): H01L21/60; H01L23/12
Domestic Patent References:
| JP2000183090A | ||||
| JP2000164617A | ||||
| JP2000164622A | ||||
| JP2000183089A | ||||
| JP2000036509A | ||||
| JP8045990A | ||||
| JP9107048A | ||||
| JP2000091339A |
Attorney, Agent or Firm:
Takao Watanuki
Horimai Kazuharu
Horimai Kazuharu