Title:
半導体記憶装置の製造方法
Document Type and Number:
Japanese Patent JP3602010
Kind Code:
B2
Abstract:
A process for manufacturing a semiconductor memory device comprises the steps of: (a) forming a tunnel oxide film, a first (1st) conductive film to be a lower floating gate, a 1st insulating film and a second (2nd) insulating film in this order on a semiconductor substrate and patterning the 2nd insulating film, the 1st insulating film, the 1st conductive film and the tunnel oxide film into a desired configuration; (b) forming a third (3rd) insulating film on the entire surface of the resulting substrate; (c) reducing the 3rd insulating film until the 2nd insulating film is exposed; (d) removing the 2nd insulating film; (e) removing the 1st insulating film while further reducing the 3rd insulating film; (f) forming a 2nd conductive film to be an upper floating gate on the 1st conductive film and the 3rd insulating film; (g) flattening the 2nd conductive film until the 3rd insulating film is exposed; and (h) forming an interlayer capacitance film and a 3rd conductive film to be a control gate on the 2nd conductive film and the 3rd insulating film, and patterning the 3rd conductive film, the interlayer capacitance film, the 2nd conductive film and the 1st conductive film to form a floating gate and the control gate.
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Inventors:
Takuji Tanigami
Application Number:
JP21897199A
Publication Date:
December 15, 2004
Filing Date:
August 02, 1999
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2000174242A | ||||
| JP11026616A | ||||
| JP10107163A | ||||
| JP10032268A | ||||
| JP9102554A | ||||
| JP8316348A | ||||
| JP8107158A | ||||
| JP8078543A | ||||
| JP6237004A |
Attorney, Agent or Firm:
Shintaro Nogawa