Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4605390
Kind Code:
B2
Abstract:
The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not accessed, the hold control transistor causes the first and second inverter circuits to form the loop connected hold circuit for statically holding data. When the memory cell is accessed, the hold control transistor causes the first and second inverter circuits to be disconnected from the loop connection for dynamically holding data, thereby preventing data corruption that would otherwise possible occur due to a read operation. Moreover, a sense amplifier circuit that uses a single bit line to read data from a memory cell is disposed in a space appearing in the memory cell array, thereby effectively using the area.
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Inventors:
Takeda Koichi
Application Number:
JP2005514917A
Publication Date:
January 05, 2011
Filing Date:
September 17, 2004
Export Citation:
Assignee:
NEC
International Classes:
G11C11/41; G11C11/412; H01L27/10; H01L27/11
Domestic Patent References:
| JPH087571A | 1996-01-12 |
Attorney, Agent or Firm:
Kenho Ikeda
Shuichi Fukuda
Takashi Sasaki
Shuichi Fukuda
Takashi Sasaki