To enable an analog multiplying circuit to perform highly linear operation with ≤2.6 V low power supply voltage.
1st analog differential signals V1p and V1n are applied to each common base of two sets of differential pairs composed of transistors Q1 to Q4. The common collector of the Q1 and Q4 is defined as an output terminal Vop, and the common collector of the Q2 and Q3 is defined as an output terminal Von. The collectors of Q11 and Q12 are respectively connected to the respective common emitters of the differential pairs. Parallel resonance circuits are respectively connected to the respective emitters of the Q11 and Q12, and R15 connects the emitters. Input circuits 101 and 102 are respectively connected to the respective bases of the Q11 and Q12, and 2nd analog differential signals V2p and V2n are inputted. The Q12 and Q14 of the circuits 101 and 102 respectively constitute current mirror circuits with the Q11 and Q13. The number of vertical mounting steps of transistors can be made to two steps and the transistors can be operated with a low power supply voltage.
JPS5591074 | DIVIDER CIRCUIT |
JP2740440 | ANALOG MULTIPLYING CIRCUIT |
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