ARITHMETIC UNIT, CORRELATION ARITHMETIC UNIT, MOVING IMAGE COMPRESSION DEVICE, AND SLIPPAGE DETECTION METHOD AND DEVICE

Japanese Patent JP3405864

B2

PROBLEM TO BE SOLVED: To carry out an operation by means of hardware of a small scale by preparing an absolute value calculation part which calculates the absolute numerical value and a code calculation part which calculates a code of the numerical value.
SOLUTION: An arithmetic unit inputs two numerical value (a) and (b) and applies the prescribed operations to these value to calculate the numerical value (c) representing the arithmetic result. Then the arithmetic unit includes an absolute value calculation part 2-1 which calculates the absolute value &verbar c&verbar of the value (c) and a code calculation part 2-2 which calculates a code sign (c) of the value (c). Then the part 2-1 inputs the signals to represent both value (a) and (b) and outputs a signal to represent the sum (&verbar a&verbar +&verbar b&verbar ) of absolute value &verbar a&verbar and &verbar b&verbar of value (a) and (b) respectively. On the other hand, the part 2-2 outputs a plus or minus signal according to the coincidence or non-coincidence between the code signs (a) and (b) of both value (a) and (b).

WO/2006/012362	SINGLE-LEVEL PARALLEL-GATED CARRY/MAJORITY CIRCUITS AND SYSTEMS THEREFROM
JP2001014140	GATE 3 STAGE 00 CUT ADDER WITH TRANSISTOR
JPS61138335	ARITHMETIC CIRCUIT OF STORAGE ELEMENT

Susumu Kawakami
Hiroaki Okamoto

JP23434395A

May 12, 2003

September 12, 1995

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富士通株式会社

G06F7/50; G06F17/15; G06G7/12; G06K9/36; G06K9/64; H04N19/42; H04N19/46; H04N19/50; H04N19/51; H04N19/597; H04N19/60; H04N19/70; (IPC1-7): G06F7/50; G06G7/12; H04N7/30; H04N7/32

JP4246722A
JP5852747A
JP6165162A
JP7162865A
JP7271985A
JP877140A

Masanori Yamada

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