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Title:
FABRICATION OF FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPH11214409
Kind Code:
A
Abstract:

To provide a method for fabricating a field-effect transistor, which prevents generation of stresses in the semiconductor film, by preparing porous regions selectively on a silicon substrate on its surface layer region, by forming compound semiconductor films on a silicon substrate, by removing the semiconductor films on the porous regions, by forming the field-effect transistor using the remaining part of the semiconductor films, and by impregnating a metal into the porous regions.

An insulating film 2 is formed on the surface of a p-type silicon substrate 1, and p+-Si regions 4 are selectively to make them porous. Then, compound semiconductor films 8, 9 and 10 are grown heteroepitaxially. Subsequently, the porous silicon regions are replaced with a metal such as Cu, so that only the porous Si regions 6 on the substrate 1 are replaced with the metal, keeping it as porous, while the silicon bridge is left unchanged. Since the compound semiconductor films are grown after the porous regions are formed in the surface layer region of the silicon substrate and the transistor is formed by using the compound semiconductor films on regions other than the porous regions, the stresses caused by the difference in lattice constant between the silicon substrate and the GaAs layers grown on the silicon substrate can be relaxed.


Inventors:
IWAMEJI KAZUAKI
Application Number:
JP1709198A
Publication Date:
August 06, 1999
Filing Date:
January 29, 1998
Export Citation:
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Assignee:
KYOCERA CORP
International Classes:
H01L21/3063; H01L21/338; H01L29/812; (IPC1-7): H01L21/338; H01L21/3063; H01L29/812