PURPOSE: To suppress the extension of physical and logical scale to minimum by constituting data transfer information by means of one storage unit adding at least data transfer destination address information and data transfer source address information and reading or writing data transfer information from a first storage means at one time by means of a data transfer device.
CONSTITUTION: As the register of data transfer control, there are a transfer information parameter register (PARM) storing a transfer information parameter, which is arranged in a random access memory, and an exclusive register. A parameter base register (ESMPBR) and an address extending register are provided as the exclusive register. ESMPBR has 24-bit length and designates the address where the transfer information parameter exists by executing comination with a vector outputted from an interrution controller. The transfer address extending register has 20-bit length and designates transfer destination and transfer source addresses by executing combination with transfer destination and transfer source address parameters.
HASHIMURA KOICHI
TSUKAMOTO TAKU
HITACHI MICROCOMPUTER SYST
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