INTEGRATED CIRCUIT WITH IMPROVED TAB TIE - AMERICAN TELEPHONE & TELEGRAPH

Title:

INTEGRATED CIRCUIT WITH IMPROVED TAB TIE

Document Type and Number:

Japanese Patent JPS6421950

Kind Code:

A

Abstract:

PURPOSE: To eliminate the need of an extra space for forming electrical connection between the source region of a field effect transistor and a doped silicon semiconductor tab region for forming the transistor by forming a metal silicide on the source region and its adjacent tab contact region. CONSTITUTION: In an integrated circuit containing both p- and n-channel field effect transistors formed on a silicon body 100, at least one transistor, for example, M20 and M21 are formed in tabs 101 and 102 formed in the body 100 and the sources 103 and 111 of the transistors M20 and M21 are electrically connected to tabs 101 and 102 with tab ties 106 and 111. The ties 106 and 112 comprises a metal silicide and are brought into contact with adjacent strongly doped contact areas 105 and 113. The silicide can be titanium silicide, tantalum silicide, molybdenum silicide, tungsten silicide, etc.

More Like This:

JPS63136661	MANUFACTURE OF SEMICONDUCTOR DEVICE
JP2005109388	SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
JP6287609	Semiconductor devices and semiconductor device design methods

Inventors:

MINNRIAN CHIEN
CHIYUN UEI REUN
DANIERU MAAKU ROOJI

Application Number:

JP15244788A

Publication Date:

January 25, 1989

Filing Date:

June 22, 1988

Export Citation:

Click for automatic bibliography generation Help

Assignee:

AMERICAN TELEPHONE & TELEGRAPH

International Classes:

H01L21/8238; H01L23/485; H01L27/092; (IPC1-7): H01L27/08

Domestic Patent References:

JPS60120571A	1985-06-28
JPS59208773A	1984-11-27

Attorney, Agent or Firm:

Masao Okabe (2 outside)

Previous Patent: サブタイトル表示方法およびサブタイトル表示デバイス

Next Patent: READ-ONLY MEMORY CODE NUMBER VERIFICATION CIRCUIT