Title:
半導体装置及び半導体装置の設計方法
Document Type and Number:
Japanese Patent JP6287609
Kind Code:
B2
Abstract:
Out of a plurality of transistors, in a power switch which controls, for each logic block, a supply and an interruption of power with respect to the each logic block, each having a gate electrode connected to a well via a contact electrode, and a body region connected to a connection portion of the well with the contact electrode via a well resistor under an element isolation insulating film, and controlling a threshold voltage by changing an electric potential applied to the body region in accordance with a signal of the gate electrode, a plurality of first transistors and a plurality of second transistors which are different from the plurality of first transistors are made to have different delay characteristics from each other between the respective connection portions of the well with the contact electrodes and the respective body regions.
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Inventors:
Youichi Yasuyama
Application Number:
JP2014120591A
Publication Date:
March 07, 2018
Filing Date:
June 11, 2014
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H01L21/8234; G06F17/50; H01L21/82; H01L21/822; H01L21/8238; H01L27/04; H01L27/088; H01L27/092; H03K19/00
Domestic Patent References:
| JP2009231312A | ||||
| JP2014038952A | ||||
| JP2012160652A | ||||
| JP2008065732A | ||||
| JP2011199113A | ||||
| JP2011199094A |
Attorney, Agent or Firm:
Takayoshi Kokubun