PURPOSE: To improve the usability of a multi-processor system by providing tag control information storage parts having addresses in the main storage device of data stored in plural central processing units (CPU).

CONSTITUTION: The tag control information storage parts 6-9 of main storage control part (MCU) 5 have the copy of the tag information storage parts 103-403 having the addresses in the main storage device 11 of data stored in the cache memories 102-403 of CPU 101-401. When a fault occurs in CPU and an action is stopped, the effect is transmitted to MCU 5, and the information is stored in a register 19. A detection means 20 judges the coincidence of CPU corresponding to the tag control information storage part and CPU stored in the register 19. When they are coincide, it is transmitted to CPU which requests a memory access, and CPU stops a processing on data which is memory access-requested. Thus, the stop of the whole system owing to the fault of one CPU is eliminated, and the usability of the multi-processor system is improved.