Title:
ウェハ上のアライメントマークを用いる半導体パッケージの製造方法
Document Type and Number:
Japanese Patent JP6741264
Kind Code:
B2
Abstract:
A method of manufacturing a semiconductor package and a semiconductor package in which positional alignment between a wafer and a substrate until the wafer is mounted and packaged on the substrate is achieved accurately. A wafer is mounted on a package substrate by using first alignment marks and D-cuts as benchmarks, and then a mold resin layer is formed on the wafer in a state in which the first alignment mark is exposed. A part of the mold resin layer is removed by using the D-cuts exposed from the mold resin layer as benchmarks, so that the first alignment marks can be visually recognized. A second alignment marks are formed on the mold resin layer by using the first alignment marks as benchmarks. A Cu redistribution layer to be conducted to a pad portion is formed on a mold resin layer by using the second alignment marks as benchmarks.
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Inventors:
Shiro Hara
Kumpuan Somawan
Fumito Imura
Kumpuan Somawan
Fumito Imura
Application Number:
JP2019510023A
Publication Date:
August 19, 2020
Filing Date:
March 28, 2018
Export Citation:
Assignee:
National Institute of Advanced Industrial Science and Technology
International Classes:
H01L21/68; H01L23/00; H01L23/12
Domestic Patent References:
| JP3068126A | ||||
| JP11260768A | ||||
| JP2009032720A | ||||
| JP2001332863A | ||||
| JP2012104757A | ||||
| JP2001144197A |
Attorney, Agent or Firm:
Patent Business Corporation Takewa International Patent Office