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Patent Searching and Data


Title:
MANUFACTURING METHOD FOR SOI WAFER
Document Type and Number:
Japanese Patent JP2003168789
Kind Code:
A
Abstract:

To provide a manufacturing method for an SOI wafer capable of reducing both the film thickness uniformity inside the wafer and the film thickness uniformity between the wafers to a sufficiently low level, even in the case that a required film thickness level of an SOI layer is extremely low.

A second Si layer 23, a first SiGe layer 22 and a first Si layer 21 are formed in the order as a multi-layer epitaxial layer on a bond wafer 2, a hydrogen high concentration layer is formed inside the second Si layer 23 by hydrogen ion implantation, and bonding heat treatment and peeling are performed. Then, a laminated body of the first Si layer 21, the first SiGe layer 22 and the peeled second Si layer 23a is connected and integrated on a silicon oxide film 3 as a peeled epitaxial layer. The peeled second Si layer 23a is selectively etched in a form of turning the first SiGe layer 22a to an etching stop layer.


Inventors:
MITANI KIYOSHI
Application Number:
JP2001364907A
Publication Date:
June 13, 2003
Filing Date:
November 29, 2001
Export Citation:
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Assignee:
SHINETSU HANDOTAI KK
International Classes:
H01L21/306; H01L21/02; H01L21/762; H01L27/12; (IPC1-7): H01L27/12; H01L21/02; H01L21/306
Attorney, Agent or Firm:
Masanori Sugawara