Title:
MAX CIRCUIT AND MIN CIRCUIT
Document Type and Number:
Japanese Patent JP3393450
Kind Code:
B2
Abstract:
PURPOSE: To reduce the error of output voltage even when the plural input voltage of a MAX circuit are equal.
CONSTITUTION: Input voltage x1 to x3 are given to the respective bases of transistors Q11 to Q13. A transistor which is given maximum input voltage of the transistors Q11 to Q13 comes into a conductive state and at its emitter, voltage obtained by subtracting base/emitter voltage from input voltage appears. This voltage is given to the emitter of a transistor Q2. For the transistors in the conductive state among the transistors Q11 to Q13 and the transistor Q2, the same amount of current is provided from,of the transistors Q31 to Q34, Q41 to Q44 and Q51 to Q54 constituting a current mirror circuit. At an output (z) connected to the collector of the transistor Q2 voltage to which base/emitter voltage is compensated, that is voltage equal to maximum input voltage, appears.
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Inventors:
Keiji Owatari
Application Number:
JP33925693A
Publication Date:
April 07, 2003
Filing Date:
December 03, 1993
Export Citation:
Assignee:
Omron Corporation
International Classes:
G06G7/12; H03K17/00; H03K19/20; (IPC1-7): G06G7/12; H03K17/00; H03K19/20
Domestic Patent References:
| JP62105281A |
Attorney, Agent or Firm:
Kenji Ushiku (1 person outside)
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