Title:
MOSFET ANALOG INTEGRATING MACHINE UTILIZING LINEARLIZED RESISTIVITY
Document Type and Number:
Japanese Patent JP3263014
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a MOSFET analog integrating machine utilizing linearlized resistivity that actualizes high-speed operation and lowers the price of the manufacture by including a 2nd current mirror which is coupled with a 1st current mirror in parallel.
SOLUTION: Through a 1st static current element and a 2nd static current element where currents almost as large as a current Im1 and a current Im2 flow, the final current IOUT is proportional to the product of voltages V1 and V2. A bipolar transistor(BJT) is used for circuit constitution for finding the difference between the two currents Im1 and Im2 flowing to MOSFETs M1 and M2 operating in a triode area. Consequently, the circuit can be constituted through a BiCMOS process which is recently generalized. Namely, simple circuit design consisting of only a small number of transistors is obtained for ASIC- implementation as conventional problem points and high-speed analog operation can be actualized in some part in an element in all application fields.
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Inventors:
Han Ichi Song
Application Number:
JP26863997A
Publication Date:
March 04, 2002
Filing Date:
October 01, 1997
Export Citation:
Assignee:
Korea Electric Communications Company
International Classes:
G06G7/14; G06F7/44; G06G7/164; G06G7/60; (IPC1-7): G06G7/14; G06G7/60
Domestic Patent References:
| JP5225365A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)