Title:
MULTI-VALUED LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP3748119
Kind Code:
B2
Abstract:
PURPOSE: To provide a multi-valued logic circuit capable of generating an output proportional to the weighted linear sum of input voltage, having sufficiently enough gain capable of optionally setting up the weight and reduced at its power consumption.
CONSTITUTION: In the multi-valued logic circuit for inputting plural multi-valued logic signals encoded so as to correspond to respective values and outputting a multi-valued logic signal corresponding to the sum of input values, a k-digit (k=0, 1, 2,...) arithmetic circuit is provided with a multi-input comparator for generating a carry signal and a multi-input amplifier for executing weighted linear voltage addition among a k-digit input, its carry signal and a (k-1)-digit carry signal, multi-input comparators A1 to A4 and multi-input amplifiers are connected to their corresponding input signals in accordance with respective capacitive coupling and the voltage gain of a multi-input voltage amplifier is determined by the ratio of the capacity of capacitive coupling to the capacity of a negative feedback circuit.
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Inventors:
▲高▼津 求
Application Number:
JP32924795A
Publication Date:
February 22, 2006
Filing Date:
December 18, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F7/50; G06G7/14; G06F7/503; G06F7/508; H03K19/20; (IPC1-7): G06G7/14; G06F7/50; H03K19/20
Domestic Patent References:
| JP58144258A | ||||
| JP4076790A |
Attorney, Agent or Firm:
Tadahiko Ito