Title:
マルチプライヤ
Document Type and Number:
Japanese Patent JP3974774
Kind Code:
B2
Abstract:
A multiplier having a simple constitution, excellent performance with respect to high-frequency characteristics and distortion characteristics, and allows low-voltage operation. Transistor Q 11 , resistors R 11 and R 12 form a common-emitter circuit. One signal of differential signal v 1 is amplified by the common-emitter circuit, and the amplified signal is input to an emitter follower composed of transistor Q 12 . The output current of the emitter follower is input through resistor R 13 into the current mirror circuit composed of transistors Q 13 and Q 14 . Output current I 5 of said current mirror circuit is input to the transistor pair of transistor Q 19 and npn transistor Q 20 . By selecting an appropriate gain for the common-emitter circuit, currents I 5 and I 6 generated in this way become independent of the base-emitter voltage, and performance is improved with respect to distortion characteristics.
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Inventors:
Yoshikatsu Matsugaki
Fukui Eizo
Fukui Eizo
Application Number:
JP2001376873A
Publication Date:
September 12, 2007
Filing Date:
December 11, 2001
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
International Classes:
G06G7/163; H03F3/45
Domestic Patent References:
| JP6215161A | ||||
| JP51033949A | ||||
| JP8056129A | ||||
| JP6139378A | ||||
| JP56162176A | ||||
| JP9198458A |
Attorney, Agent or Firm:
Takahisa Sato