To provide a nonvolatile storage device, an integrated circuit device, and an electronic apparatus capable of improving endurance characteristics or the like by suppressing the generation of an over-erase bit.
The nonvolatile storage device includes a memory cell array including a plurality of electrically rewritable and erasable nonvolatile memory cells M11 to M44, and an erase control circuit ERCN controlling an erase operation for the memory cells to be erased from among the plurality of nonvolatile memory cells. The erase control circuit ERCN performs first erase operation control for setting the bit lines BL1 to BL4 corresponding to the memory cells to be erased in a floating state when there are many memory cells to be erased. When there are few memory cells to be erased, the erase control circuit performs second erase operation control for setting the bit lines BL1 to BL4 corresponding to the memory cells to be erased at a low potential power source voltage VSS.
| JPS61150195 | MEMORY CONTENT STORING METHOD |
| JP6084246 | 3D independent double gate flash memory |
TOKUDA YASUNOBU
KOBAYASHI HITOSHI
Takekoshi Noboru
Yasushi Kuroda