To prevent an access time from lowering by ending pre-charge of a data line of an even number before a read-out circuit starts to operate at a read resetting.

A pre-charge circuit 16 is provided with the circuit pre-charging the data line DL1 connected to a read bit line group of the even numbered at the read resetting time. In the case that this circuit is not provided, when a memory cell of e.g. an even number address A is read out, an L level signal of a read resetting signal RRES* is received, the data line DL1 for the even number exists on a voltage value corresponding to the data in the memory cell of the address A, and is not pre-charged until the memory cell of 0 address selected after resetting is read out. Thus, by that the pre-charge circuit 16 pre-charges the data line DL1 connected to a bit line RBL0 for the 0 address at the resetting time, the delay of the access time and erroneous writing are prevented.