Title:
RESISTANCE ELEMENT AND METHOD FOR MANUFACTURING THE SAME, BIAS CIRCUIT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2005203514
Kind Code:
A
Abstract:
To provide a bias circuit wherein the bias current is kept constant even in the fluctuations due to process variation in the field effect transistor threshold, and to provide a resistance element for use with the bias circuit.
The resistance of the channel layer of a field effect transistor (FET) serves as a second resistance element for use with the bias circuit. A p-type impurity region 17b for adjusting channel resistance is formed in the upper layer of the channel layer 14. The p-type impurity region 17b constituting the resistance adjusting section is formed into a slit-shape pattern stretching in the direction of current flow in the channel 14 (serving as the channel resistance for the second resistance element).
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Inventors:
NAKAMURA MITSUHIRO
Application Number:
JP2004007202A
Publication Date:
July 28, 2005
Filing Date:
January 14, 2004
Export Citation:
Assignee:
SONY CORP
International Classes:
H01L27/04; H01L21/337; H01L21/338; H01L21/822; H01L27/095; H01L29/778; H01L29/808; H01L29/812; (IPC1-7): H01L21/822; H01L21/337; H01L21/338; H01L27/04; H01L27/095; H01L29/778; H01L29/808; H01L29/812
Attorney, Agent or Firm:
Takahisa Sato