Title:
SEMICONDUCTOR ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3706869
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform polynomial addition processing fast with small area by adding all the bits of data in binary notation which are inputted at the same time at a time and converting an analog signal which has linear relation with the addition result into a digital signal.
SOLUTION: Input terminals 301-307 are coupled with floating electrodes 311-317 through capacitors to generate analog voltages to be supplied to the floating electrodes as an addition means of input bits. The floating electrodes are the gate electrodes of neuron MOS transistors and neuron MOS inverter circuits 321-327 which are different in threshold value are constituted. Then the inverter circuit 321 outputs 0 to an output terminal 331 when the batch addition result is ≥1, the inverter circuit 322 outputs 0 to a terminal 322 when the batch addition result is ≥2, and so on the inverter circuits 323-326 output 0; and the inverter circuit 327 outputs 0 to a terminal 337 when the batch addition result is ≥7, and consequently 7 input bit data are added together at a time.
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Inventors:
Tadahiro Ohmi
Makoto Imai
Koji Kotani
Nao Shibata
Makoto Imai
Koji Kotani
Nao Shibata
Application Number:
JP8594896A
Publication Date:
October 19, 2005
Filing Date:
March 13, 1996
Export Citation:
Assignee:
Tadahiro Ohmi
Nao Shibata
UCT Co., Ltd.
I & F Co., Ltd.
Nao Shibata
UCT Co., Ltd.
I & F Co., Ltd.
International Classes:
G06F7/509; G06F7/49; G06F7/501; G06G7/14; H01L27/10; H03K19/20; H03M1/00; (IPC1-7): G06F7/50; G06G7/14; H01L27/10; H03K19/20
Domestic Patent References:
| JP5150947A | ||||
| JP5341963A |
Foreign References:
| WO1992016971A1 |
Attorney, Agent or Firm:
Hisao Fukumori
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