SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Title:

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Document Type and Number:

Japanese Patent JP2007157934

Kind Code:

A

Abstract:

To remarkably shorten the entire length of a process while suppressing an increase in propagation delay by mixedly mounting a p-channel transistor and an n-channel transistor on different semiconductor layers.

The n-channel transistor (p-channel transistor) is formed on a semiconductor substrate 11, an insulation film 31 having a concave portion 32 formed thereon is formed on the n-channel transistor (p-channel transistor), an amorphous semiconductor layer 33 is formed on the insulation film 31 so that the inside of the concave portion 32 is filled, and the amorphous semiconductor layer 33 is irradiated with laser to melt and crystallize the amorphous semiconductor layer 33. In this way, a substantially signal crystal semiconductor particle 34 is formed around the concave portion 32, and the p-channel transistor (n-channel transistor) is formed on the substantially single crystal semiconductor particle 34.

More Like This:

JP2013153040	SEMICONDUCTOR DEVICE MANUFACTURING METHOD
JP2004079748	INSULATED GATE FIELD EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD
WO/2010/047105	SPUTTERING TARGET FOR FORMING THIN FILM TRANSISTOR WIRING FILM

Inventors:

SHIMADA HIROYUKI
MORI KATSUMI

Application Number:

JP2005349588A

Publication Date:

June 21, 2007

Filing Date:

December 02, 2005

Export Citation:

Click for automatic bibliography generation Help

Assignee:

SEIKO EPSON CORP

International Classes:

H01L29/786; H01L21/20; H01L21/265; H01L21/28; H01L21/336; H01L21/8234; H01L21/8238; H01L27/00; H01L27/088; H01L27/092

Attorney, Agent or Firm:

Tetsuya Mori
Yoshiaki Naito
Cui Shu Tetsu

Previous Patent: WAFER CLEANING DEVICE

Next Patent: SUBSTRATE PROCESSING DEVICE, AND SUBSTRATE PROCESSING METHOD