Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3251109
Kind Code:
B2
Abstract:
PURPOSE: To suppress increasing of a chip area to the minimum and to perform relieving of good efficiency in a memory reading device having an error detection correcting circuit.
CONSTITUTION: A defective address and a check bit 2 are previously stored by a fuse, when coincidence of external input addresses Axa-Axn and the stored defective address is detected by a defective address coincidence detecting circuit 1, the check bit 2 is selected by a word line WD1, data is corrected by an error detection correcting circuit 5 and outputted to an output circuit 6. When the external addresses do not coincide with the stored defective address, read out data is not passed through the error detection correcting circuit 5, and directly outputted to the output circuit 6. That is, increasing of a chip area can be suppressed and relieving of good efficiency can be performed by providing a check bit for only a defective address.
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Inventors:
Masaru Hashinaga
Application Number:
JP27878393A
Publication Date:
January 28, 2002
Filing Date:
November 09, 1993
Export Citation:
Assignee:
Kyushu NEC Corporation
International Classes:
G06F11/10; G11C17/14; G11C29/00; G11C29/42; (IPC1-7): G11C29/00
Domestic Patent References:
| JP428098A | ||||
| JP4206100A | ||||
| JP4372798A | ||||
| JP7111096A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)