Title:
SEMICONDUCTOR INTEGRATED CIRCUIT, MANUFACTURE THEREOF, SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3519589
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduced the leakage current due to fine defects because of contact of materials different in vol. expansion coefficient or etching damage remaining on inner walls of isolation trenches for isolating elements, by filling the isolation trenches with fluoride.
SOLUTION: STI 12 for isolating elements formed on active semiconductor regions 30, 31 of a semiconductor substrate 1 has an Si oxide film 32 on a trench side wall, and Si oxide 34 near the boundary of a main plane of the substrate 1. The trench is filled with SiOF 35 extending vertically to the paper like a band. For forming STI 2, fine defects may occur at the material interface because of etching damage of the inner wall of the trench or contact of the substrate 1 to the silicon oxide film 32 different in vol. expansion coefficient, but F ions produced at the time of burying SiOF 35 bond with dangling bonds of Si atoms and hence lessen, thus reducing the leak current.
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Inventors:
Kunikiyo, Tatsuya
Application Number:
JP35491897A
Publication Date:
April 19, 2004
Filing Date:
December 24, 1997
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/76; H01L21/28; H01L21/3205; H01L21/336; H01L21/762; H01L21/768; H01L21/8242; H01L23/522; H01L27/108; H01L29/423; H01L29/49; H01L29/78; (IPC1-7): H01L21/76; H01L21/768
Attorney, Agent or Firm:
吉田 茂明 （外２名）
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