Title:
半導体メモリの製造方法
Document Type and Number:
Japanese Patent JP7154114
Kind Code:
B2
Abstract:
A method of manufacturing a semiconductor memory includes: forming a first lamination on a substrate; forming a first hole through the first lamination; embedding a first sacrificial material including a thermally decomposable organic material in the first hole; forming a recess at an upper portion of the first hole; forming an oxide film in the recess; removing the first sacrificial material under the oxide film; embedding a second sacrificial material on the oxide film in the recess; forming a second lamination on the first lamination and the second sacrificial material; forming a second hole through the second lamination at a position corresponding to the first hole by etching the second lamination in an extension direction of the first hole; and removing the oxide film and the second sacrificial material.
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Inventors:
Lee
Tatsuya Yamaguchi
Shuji Nozawa
Nagisa Sato
Tatsuya Yamaguchi
Shuji Nozawa
Nagisa Sato
Application Number:
JP2018213838A
Publication Date:
October 17, 2022
Filing Date:
November 14, 2018
Export Citation:
Assignee:
東京エレクトロン株式会社
International Classes:
H01L27/11582; H01L21/3065; H01L21/336; H01L27/11556; H01L29/788; H01L29/792
Domestic Patent References:
| JP2006041186A | ||||
| JP2018170473A |
Foreign References:
| US9449982 | ||||
| WO2016158697A1 | ||||
| US20130059422 |
Attorney, Agent or Firm:
Sakai International Patent Office
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