PURPOSE: To enable a first and a third wiring laid out in a channel region to be lessened in number by a method wherein a first and a second wiring are laid out after the third wiring is laid out at a certain position where it can be laid out.

CONSTITUTION: A region where a contact hole NC which connects a third wiring LC to a second wiring LB can be formed is found on a cell 1. A third wiring LC connected to the contact hole NC is laid out on the cell 1. A first wiring LA is laid out between cell rows 2, and the second wiring LB is laid out vertical to the cell row 2. Furthermore, the current density of the contact hole NC is calculated, and the wirings LA to LC are laid out again so as to optimize the current density of each contact hole NC, whereby a three-layered wiring is laid out. By this setup, a chip can be lessened in size.