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Patent Searching and Data


Title:
DOUBLE LOOP PLL CIRCUIT
Document Type and Number:
Japanese Patent JPS60113530
Kind Code:
A
Abstract:

PURPOSE: To obtain a simpel PLL circuit which uses no arithmetic amplifier by applying the low-pass filter (LPF) output of a main loop and the LPF output of a secondary loop to both ends of a variable capacity diode connected in series or parallel to a crystal oscillator.

CONSTITUTION: An input signal ein is compared with the output of a voltage control oscillator 4 by phase comparators 1a and 1b and delivered to LPFs 2a and 2b in the form of error outputs a and b respectively. The outputs Ea and Eb of the LPFs 2a and 2b are applied to both ends of a variable capacity diode 40 connected in series to a crystal oscillator 41. Thus the diode 40 is controlled by the differential voltage. As a result, the oscillation frequency and the phase of the oscillator 4 are controlled by the differential voltage between outputs of both comparators.


Inventors:
KAJIWARA MASANORI
OGISO MASAAKI
Application Number:
JP22104483A
Publication Date:
June 20, 1985
Filing Date:
November 24, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03L7/08; H03L7/087; (IPC1-7): H03L7/06
Domestic Patent References:
JPS58107727A1983-06-27
Attorney, Agent or Firm:
Sadaichi Igita