To provide a transverse junction field effect transistor wherein leakage current can be prevented and sufficient voltage-withstanding ability can be achieved.
In a transverse JFET 10, a buffer layer 11 is disposed on a main surface of an SiC substrate 1 and includes p-type impurities. A channel layer 12 is disposed on the buffer layer 11 and includes n-type impurities at a concentration higher than the concentration of p-type impurities in the buffer layer 11. An n-type source region 15 and a drain region 16 are formed separate from one another in a surface layer of the channel layer 12, and a p-type gate region 17 is positioned between the source region 15 and the drain region 16 in the surface layer of the channel layer 12. A barrier region 13 is disposed in an area below the gate region 17 in a boundary region of the channel layer 12 and the buffer layer 11, and contains p-type impurities at a higher concentration than the concentration of the p-type impurities in the buffer layer 11.
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HARADA MAKOTO
NAMIKAWA YASUO
| JP2003068762A | 2003-03-07 | |||
| JPS57190365A | 1982-11-22 | |||
| JPS51102580A | 1976-09-10 | |||
| JP2000138233A | 2000-05-16 |
| WO2004112150A1 | 2004-12-23 |
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