The layout design of small and strong level shifter

Title:

The layout design of small and strong level shifter

Document Type and Number:

Japanese Patent JP5940660

Kind Code:

B2

Abstract:

Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.

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Inventors:

Animated Datta
William James Goodall Third

Application Number:

JP2014520346A

Publication Date:

June 29, 2016

Filing Date:

July 12, 2012

Export Citation:

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