Title:
MULTILAYER CERAMIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2024/029150
Kind Code:
A1
Abstract:
Provided is a multilayer ceramic capacitor that can suppress the occurrence of peeling between internal electrode layers at the ends of a laminated body, even if a dielectric layer etc. is made thin. A multilayer ceramic capacitor according to the present invention comprises: a laminated body that has a plurality of dielectric layers which are laminated and a plurality of internal electrode layers which are laminated on the dielectric layers, and that has a first main surface and second main surface which are opposite from each other in the lamination direction, a first end surface and a second end surface which are opposite from each other in the length direction orthogonal to the lamination direction, and a first side surface and a second side surface which are opposite from each other in the width direction orthogonal to the lamination direction and the length direction; a first external electrode that is disposed on the first end surface; and a second external electrode that is disposed on the second end surface. The plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers which are disposed alternatingly on different dielectric layers. The plurality of first internal electrode layers have a plurality of first counter electrode parts that are opposite from the second internal electrode layers and a plurality of first lead-out parts that respectively extend from the plurality of first counter electrode parts and that lead out to the first end surface. The second internal electrode layers have a plurality of second counter electrode parts that are opposite from the first internal electrode layers and a plurality of second lead-out parts that respectively extend from the plurality of second counter electrode parts and that lead out to the first side surface. The first lead-out parts have first connection parts connected so as to span to at least two first lead-out parts in the lamination direction, between first lead-out parts positioned on differing dielectric layers of at least the first main surface side or at least the second main surface side. The second lead-out parts have second connection parts connected so as to span to at least two second lead-out parts in the lamination direction, between second lead-out parts positioned on differing dielectric layers of at least the first main surface side or at least the second main surface side.
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Inventors:
NISHIBAYASHI KAZUHIRO (JP)
KOYAMA YUKI (JP)
KOYAMA YUKI (JP)
Application Number:
PCT/JP2023/017200
Publication Date:
February 08, 2024
Filing Date:
May 02, 2023
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G4/30
Foreign References:
| JPS63172416A | 1988-07-16 | |||
| JPH02251120A | 1990-10-08 | |||
| JP2012104736A | 2012-05-31 | |||
| JPH05335175A | 1993-12-17 |
Attorney, Agent or Firm:
OKADA, Masahiro (JP)
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