Title:
SCANNING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2013/084364
Kind Code:
A1
Abstract:
A scanning circuit includes: a plurality of first scanning flip-flops that include a first logic circuit and receive a plurality of control signals in addition to a scanning input signal and a data input signal to be latched; and a plurality of second scanning flip-flops that include a second logic circuit and receive the plurality of control signals in addition to the scanning input signal and the data input signal to be latched. The first scanning flip-flops and the second scanning flip-flops are connected in series, the plurality of control signals include only a 1-bit reset signal and control signals having a purpose other than initialization, and by setting the plurality of control signals to a set of predetermined logic values, the first scanning flip-flops are initialized to 0 by the first logic circuit and the second scanning flip-flops are initialized to 1 by the second logic circuit.
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Inventors:
SUGIYAMA ITSUMI (JP)
Application Number:
PCT/JP2011/078614
Publication Date:
June 13, 2013
Filing Date:
December 09, 2011
Export Citation:
Assignee:
FUJITSU LTD (JP)
SUGIYAMA ITSUMI (JP)
SUGIYAMA ITSUMI (JP)
International Classes:
G01R31/28
Foreign References:
| JPH01265174A | 1989-10-23 | |||
| JP2004134628A | 2004-04-30 |
Attorney, Agent or Firm:
ITOH, TADAHIKO (JP)
Tadahiko Ito (JP)
Tadahiko Ito (JP)
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Claims: