Title:
半導体装置
Document Type and Number:
Japanese Patent JP5301020
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent a threshold voltage of a memory cell from being difficult to fall down due to repeating of data rewriting.SOLUTION: Each memory cell MC of a semiconductor device 1 includes a first transistor (for reading) TRA and a second transistor (for writing) each having a common floating gate FG. A control circuit 11 detects short circuit between sub-bit lines SBL_R and SBL_P connected to the first and second transistors, respectively by comparing current caused to flow to the memory cell when energizing one transistor with current caused to flow to the memory cell when energizing the both transistors.
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Inventors:
Shinji Kawai
Fine gold
Hisaya Shigehiro
Kouhei Hashimoto
Fine gold
Hisaya Shigehiro
Kouhei Hashimoto
Application Number:
JP2012163839A
Publication Date:
September 25, 2013
Filing Date:
July 24, 2012
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C29/12; G11C16/02; G11C16/04; G11C17/00
Domestic Patent References:
| JP63150959A | ||||
| JP60246099A | ||||
| JP2005025800A | ||||
| JP2007280446A |
Attorney, Agent or Firm:
Fukami patent office